Cu Resistivity Scaling Limits for 20nm Copper Damascene Lines

J. Van Olmen, S. List, Z. Tokei, L. Carbonell, S. Brongersma, H. Volders, E. Kunnen, N. Heylen, I. Ciofi, A. Khandelwal, J. Gelatos, T. Mandrekar, P. Boelen
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引用次数: 6

Abstract

Two of the most important questions concerning the future of interconnects are 1) how scalable is the damascene process to extremely narrow trenches and 2) what is the resistivity of Cu in these trenches? We attempt to answer both these questions through the generation of high aspect ratio, rectangular cross section trenches as narrow as 20 nm using a novel sacrificial Si FIN process flow. To fill such aggressive geometries, we also explore advanced PVD and ALD barrier and seed processes. We find significant electrical yields for 25 to 35 nm test structures with resistivities as predicted by sidewall scattering models.
20nm铜大马士革线的铜电阻率结垢极限
关于未来互连的两个最重要的问题是:1)damascene工艺在极窄沟槽中的可扩展性如何? 2)这些沟槽中的Cu电阻率是多少?我们试图通过使用一种新的牺牲Si FIN工艺流程产生窄至20 nm的高纵横比矩形横截面沟槽来回答这两个问题。为了填补这些具有侵略性的几何形状,我们还探索了先进的PVD和ALD屏障和种子工艺。我们发现25至35 nm测试结构的显著电产率,其电阻率与侧壁散射模型预测的一致。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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