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2007 IEEE International Interconnect Technology Conferencee最新文献

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A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative 用于RC互连替代方案的低延迟、高能效片上LVDS传输线互连
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382387
H. Ito, J. Seita, T. Ishii, H. Sugita, K. Okada, K. Masu
{"title":"A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative","authors":"H. Ito, J. Seita, T. Ishii, H. Sugita, K. Okada, K. Masu","doi":"10.1109/IITC.2007.382387","DOIUrl":"https://doi.org/10.1109/IITC.2007.382387","url":null,"abstract":"This paper demonstrates a low voltage differential signaling (LVDS)-type on-chip transmission line (TL) interconnect to solve delay issues on a global interconnect. The proposed TL interconnect can achieve 10 Gbps signaling with 2.7 mW power consumption. The on-chip LVDS TL interconnect has the best power efficiency for on-chip interconnects at over 1 mm. Delay variation of the TL interconnect is 89 % smaller than that of the conventional RC interconnect.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131759503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors 尺寸效应和铜互连工艺变化对单核和多核微处理器最大关键路径延迟的影响
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382346
G. Lopez, R. Murali, R. Sarvari, K. Bowman, J. Davis, J. Meindl
{"title":"The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors","authors":"G. Lopez, R. Murali, R. Sarvari, K. Bowman, J. Davis, J. Meindl","doi":"10.1109/IITC.2007.382346","DOIUrl":"https://doi.org/10.1109/IITC.2007.382346","url":null,"abstract":"We present a new closed-form compact model for conductor resistivity considering size effects, line-edge roughness and CMP dishing. Using this model, Monte Carlo simulations quantify the impact of interconnect variations on maximum critical path delay distributions for future technologies. Results indicate LER amplitudes start to become a substantial percentage of the nominal effective line-width dimension (2016 to 2020), leading to an increase in the conductor resistivity. Moreover, multi-core systems exhibit better tolerance to interconnect variations due to their short-wire architecture - as much as a 35% reduction for the maximum critical path delay mean degradation and standard deviation is observed for the year 2020 with a 14 nm half-pitch.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127255806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
The Impact of Multi-Core Architectures on Design of Chip-Level Interconnect Networks 多核架构对芯片级互连网络设计的影响
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382371
D. Sekar, J. Meindl
{"title":"The Impact of Multi-Core Architectures on Design of Chip-Level Interconnect Networks","authors":"D. Sekar, J. Meindl","doi":"10.1109/IITC.2007.382371","DOIUrl":"https://doi.org/10.1109/IITC.2007.382371","url":null,"abstract":"This paper studies the impact of multi-core architectures on design of chip-level interconnect networks. A dual core 3 GHz processor is found to require 23% fewer metal levels than a single core 6 GHz processor while a quad core 1.5 GHz processor needs 38% fewer interconnect levels than the single core 6 GHz processor. This is because lower frequency chips can use smaller pitch wires and pack the wiring into a fewer number of metal levels.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117318159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Comparison of Voltage Ramp and Time Dependent Dielectric Breakdown Tests for Evaluation of 45nm Low-k SiCOH Reliability 45nm低k SiCOH可靠性评估的电压斜坡和时间相关介电击穿试验比较
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382370
F. Chen, P. McLaughlin, J. Gambino, J. Gill
{"title":"A Comparison of Voltage Ramp and Time Dependent Dielectric Breakdown Tests for Evaluation of 45nm Low-k SiCOH Reliability","authors":"F. Chen, P. McLaughlin, J. Gambino, J. Gill","doi":"10.1109/IITC.2007.382370","DOIUrl":"https://doi.org/10.1109/IITC.2007.382370","url":null,"abstract":"A comparison of the relationship between voltage ramp dielectric breakdown (VRDB) test and constant-voltage time-dependent dielectric breakdown (TDDB) stress has been performed as part of a 45 nm low-k SiCOH reliability evaluation. Although some correlation was observed between VRDB and TDDB, it was found that the fast VRDB test can't replace TDDB to evaluate true long-term time-dependent behavior, which is important for reliability qualification. However, with the combination of VRDB and TDDB, a more comprehensive reliability assessment of low- k dielectric breakdown could be achieved. Finally, a novel, non-destructive spacing determination methodology is proposed and an excellent agreement between the extracted spacing and measured spacing is demonstrated.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121106437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Strategies of RC Delay Reduction in 45 nm BEOL Technology 45nm BEOL技术RC延迟降低策略
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382383
H. Kudo, H. Ochimizu, A. Tsukune, S. Okano, K. Naitou, M. Sakamoto, S. Takesako, T. Shirasu, A. Asneil, N. Idani, K. Sugimoto, S. Ozaki, Y. Nakata, T. Owada, H. Watatani, N. Ohara, N. Ohtsuka, M. Sunayama, H. Sakai, T. Tabira, A. Matsuura, Y. Iba, Y. Mizushima, H. Matsuyama, Y. Suzuki, N. Shimizu, K. Yanai, M. Nakaishi, T. Futatsugi, I. Hanyu, T. Nakamura, T. Sugii
{"title":"Strategies of RC Delay Reduction in 45 nm BEOL Technology","authors":"H. Kudo, H. Ochimizu, A. Tsukune, S. Okano, K. Naitou, M. Sakamoto, S. Takesako, T. Shirasu, A. Asneil, N. Idani, K. Sugimoto, S. Ozaki, Y. Nakata, T. Owada, H. Watatani, N. Ohara, N. Ohtsuka, M. Sunayama, H. Sakai, T. Tabira, A. Matsuura, Y. Iba, Y. Mizushima, H. Matsuyama, Y. Suzuki, N. Shimizu, K. Yanai, M. Nakaishi, T. Futatsugi, I. Hanyu, T. Nakamura, T. Sugii","doi":"10.1109/IITC.2007.382383","DOIUrl":"https://doi.org/10.1109/IITC.2007.382383","url":null,"abstract":"According to the 45 nm BEOL technology node, we demonstrated that a homogeneous interlayer dielectric with dielectric constant of 2.25 has a substantial advantage in terms of RC delay reduction compared to other potential architectures such as hybrid and tri-level dielectrics. Combination of the homogeneous interlayer dielectric and ultra-thinned barrier metal lowered the RC delay to 86 % compared to that listed in the ITRS 2006 update.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125852806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Multi-Level Cu Interconnects Integration and Characterization with Air Gap as Ultra-Low K Material Formed using a Hybrid Sacrificial Oxide / Polymer Stack 采用牺牲氧化物/聚合物复合材料形成的超低K材料的气隙多层铜互连集成和表征
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382348
L. Gosset, F. Gaillard, D. Bouchu, R. Gras, J. de Pontcharra, S. Orain, O. Cueto, P. Lyan, O. Louveau, G. Passemard, J. Torres
{"title":"Multi-Level Cu Interconnects Integration and Characterization with Air Gap as Ultra-Low K Material Formed using a Hybrid Sacrificial Oxide / Polymer Stack","authors":"L. Gosset, F. Gaillard, D. Bouchu, R. Gras, J. de Pontcharra, S. Orain, O. Cueto, P. Lyan, O. Louveau, G. Passemard, J. Torres","doi":"10.1109/IITC.2007.382348","DOIUrl":"https://doi.org/10.1109/IITC.2007.382348","url":null,"abstract":"The introduction of air gaps in multi-level Cu interconnect stacks will be mandatory to achieve high performance signal propagation characteristics for advanced technology node. In this paper, air cavities were successfully introduced in a two-metal level interconnect stack using respectively a polymer and a sacrificial SiO2 at via and metal levels. Combined with a diluted HF chemistry and specific HF diffusion pathways patterned in a SiC liner, the ability to localize the introduction of air cavities in a dedicated large electrical area was demonstrated. Electrical characteristics and mechanical simulations demonstrated the interest of the approach with respect to ultra-low K material integration issues.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"40 22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128472129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Technology and Design Cooperation: High-K MIM Capacitors for Microprocessor, IO, and Clocking 技术与设计合作:用于微处理器、IO和时钟的高k MIM电容器
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382356
H. Sánchez, O. Mandhana, B. Johnstone, D. Roberts, J. Siegel, B. Melnick, M. Celik, M. Baker, J. Hayden, B. Min, J. Edgerton, B. White
{"title":"Technology and Design Cooperation: High-K MIM Capacitors for Microprocessor, IO, and Clocking","authors":"H. Sánchez, O. Mandhana, B. Johnstone, D. Roberts, J. Siegel, B. Melnick, M. Celik, M. Baker, J. Hayden, B. Min, J. Edgerton, B. White","doi":"10.1109/IITC.2007.382356","DOIUrl":"https://doi.org/10.1109/IITC.2007.382356","url":null,"abstract":"In this work a high-K MIM capacitor module has been described that has been shown to improve the frequency of microprocessors, stabilize the power supply noise of IOs and positively affect the resulting data eyes for high speed IO. Furthermore, improvements in high speed clocking are also achieved.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130997892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and Optimization for Nanoscale Power Distribution Networks in Gigascale Systems 千兆级系统中纳米级配电网络的设计与优化
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382386
R. Sarvari, A. Naeemi, P. Zarkesh-Ha, J. Meindl
{"title":"Design and Optimization for Nanoscale Power Distribution Networks in Gigascale Systems","authors":"R. Sarvari, A. Naeemi, P. Zarkesh-Ha, J. Meindl","doi":"10.1109/IITC.2007.382386","DOIUrl":"https://doi.org/10.1109/IITC.2007.382386","url":null,"abstract":"For the first time, an optimization methodology has been presented for power distribution interconnects at the local level. For a given IR drop budget, compact models are presented for the optimal widths of power and ground lines in the first two metal levels for which the total metal area used for power distribution is minimized. Wire widths and thicknesses at the end of the ITRS are projected to scale down to 14 nm, and size effects are expected to increase copper resistivity by more than 4 times. Either a 3 times increase in wiring area for local power lines or a 2 times decrease in the power via pitch is necessary to compensate for size effects.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134103796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The critical role of the metal / porous low-k interface in post direct CMP defectivity generation and resulting ULK surface and bulk hydrophilisation 金属/多孔低k界面在直接CMP缺陷产生和由此产生的ULK表面和体亲水性中的关键作用
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382379
Y. Travaly, F. Sinapi, N. Heylen, A. Humbert, M. Delande, R. Caluwaert, J. de Mussy, G. Vereecke, M. Baklanov, F. Iacopi, J.L. Hernandez, G. Beyer, P. Fischer
{"title":"The critical role of the metal / porous low-k interface in post direct CMP defectivity generation and resulting ULK surface and bulk hydrophilisation","authors":"Y. Travaly, F. Sinapi, N. Heylen, A. Humbert, M. Delande, R. Caluwaert, J. de Mussy, G. Vereecke, M. Baklanov, F. Iacopi, J.L. Hernandez, G. Beyer, P. Fischer","doi":"10.1109/IITC.2007.382379","DOIUrl":"https://doi.org/10.1109/IITC.2007.382379","url":null,"abstract":"Surface hydrophilisation of pristine low-k (ULK) is known as a CMP-induced damage mechanism. This phenomenon already enhanced by several factors (e.g. mechanical polishing action, solid content in the slurry, pH of the slurry solution, presence of organic residues, etc ...) extends to bulk hydrophilisation when polishing metal/ULK systems. The degree of bulk hydrophilisation depends on the nature of the selected metal/low-k combination, the metal being either a hard mask (for low damage patterning purposes) or a Cu diffusion barrier. The phenomenon is more or less pronounced depending on the nature of the overlaying metal film (Ta>TaN>Ti>TiN). It also correlates with the post CMP defects generation and more specifically with the presence of scratches with depths ranging from ~178 nm down to ~6 nm as measured with a 0.19 mum tip depending on the metallic layer. These scratches can be reduced in number and depth by overpolishing leading thereby to reduced hydrophilicity. Besides selecting properly the overlaying metal film, UV curing the ULK for mechanical properties improvement and/or engineering the metal/ULK interface by inserting an ultra-thin dielectric layer with higher mechanical properties to prevent the metal from contacting the low-k surface significantly limits the direct CMP-induced bulk hydrophylisation.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133277328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Self-Formed Barrier Technology using CuMn Alloy Seed for Copper Dual-Damascene Interconnect with porous-SiOC/porous-PAr Hybrid Dielectric 多孔sioc /多孔par混合介质铜双大马士革互连用CuMn合金种子自形成势垒技术
2007 IEEE International Interconnect Technology Conferencee Pub Date : 2007-06-04 DOI: 10.1109/IITC.2007.382332
T. Watanabe, H. Nasu, G. Minamihaba, N. Kurashima, A. Gawase, M. Shimada, Y. Yoshimizu, Y. Uozumi, H. Shibata
{"title":"Self-Formed Barrier Technology using CuMn Alloy Seed for Copper Dual-Damascene Interconnect with porous-SiOC/porous-PAr Hybrid Dielectric","authors":"T. Watanabe, H. Nasu, G. Minamihaba, N. Kurashima, A. Gawase, M. Shimada, Y. Yoshimizu, Y. Uozumi, H. Shibata","doi":"10.1109/IITC.2007.382332","DOIUrl":"https://doi.org/10.1109/IITC.2007.382332","url":null,"abstract":"Self-formed barrier technology using copper (Cu) manganese (Mn) alloy seed was applied for Cu dual-damascene interconnect with porous-SiOC/porous-PAr (k=2.3) hybrid dielectric for the first time. More than 90% yield for wiring and via-chain was obtained. 70% reduction in via resistance was confirmed compared with the conventional process. To estimate the moisture resistance property of self-formed barrier, via resistance change was measured with dummy density pattern. As the result, it was found that the resistance change ratio of via for self-formed barrier does not depend on the dummy density, probably due to the high moisture resistance property of self-formed oxide barrier. In addition, outgas at high temperature is found to be essential to form self-formed barrier for porous dielectric.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114307986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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