{"title":"多核架构对芯片级互连网络设计的影响","authors":"D. Sekar, J. Meindl","doi":"10.1109/IITC.2007.382371","DOIUrl":null,"url":null,"abstract":"This paper studies the impact of multi-core architectures on design of chip-level interconnect networks. A dual core 3 GHz processor is found to require 23% fewer metal levels than a single core 6 GHz processor while a quad core 1.5 GHz processor needs 38% fewer interconnect levels than the single core 6 GHz processor. This is because lower frequency chips can use smaller pitch wires and pack the wiring into a fewer number of metal levels.","PeriodicalId":403602,"journal":{"name":"2007 IEEE International Interconnect Technology Conferencee","volume":"77 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"The Impact of Multi-Core Architectures on Design of Chip-Level Interconnect Networks\",\"authors\":\"D. Sekar, J. Meindl\",\"doi\":\"10.1109/IITC.2007.382371\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper studies the impact of multi-core architectures on design of chip-level interconnect networks. A dual core 3 GHz processor is found to require 23% fewer metal levels than a single core 6 GHz processor while a quad core 1.5 GHz processor needs 38% fewer interconnect levels than the single core 6 GHz processor. This is because lower frequency chips can use smaller pitch wires and pack the wiring into a fewer number of metal levels.\",\"PeriodicalId\":403602,\"journal\":{\"name\":\"2007 IEEE International Interconnect Technology Conferencee\",\"volume\":\"77 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE International Interconnect Technology Conferencee\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2007.382371\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE International Interconnect Technology Conferencee","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2007.382371","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The Impact of Multi-Core Architectures on Design of Chip-Level Interconnect Networks
This paper studies the impact of multi-core architectures on design of chip-level interconnect networks. A dual core 3 GHz processor is found to require 23% fewer metal levels than a single core 6 GHz processor while a quad core 1.5 GHz processor needs 38% fewer interconnect levels than the single core 6 GHz processor. This is because lower frequency chips can use smaller pitch wires and pack the wiring into a fewer number of metal levels.