H. Ito, J. Seita, T. Ishii, H. Sugita, K. Okada, K. Masu
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A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative
This paper demonstrates a low voltage differential signaling (LVDS)-type on-chip transmission line (TL) interconnect to solve delay issues on a global interconnect. The proposed TL interconnect can achieve 10 Gbps signaling with 2.7 mW power consumption. The on-chip LVDS TL interconnect has the best power efficiency for on-chip interconnects at over 1 mm. Delay variation of the TL interconnect is 89 % smaller than that of the conventional RC interconnect.
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