IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers最新文献_第4页

A 12 b 500 ns subranging ADC a12b500ns分段ADC

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48215

M. Kolluri

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引用次数: 15

200 Mb wafer memory 200mb晶圆存储器

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48272

N. MacDonald, G. Neish, A. Sinclair, F. Baba, T. Tatematsu, K. Hirawa, K. Miyasaka

{"title":"200 Mb wafer memory","authors":"N. MacDonald, G. Neish, A. Sinclair, F. Baba, T. Tatematsu, K. Hirawa, K. Miyasaka","doi":"10.1109/ISSCC.1989.48272","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48272","url":null,"abstract":"The realization of a high-capacity whole-wafer memory is described, including wafer configuration, chip architecture, process technology, and performance. The wafer is essentially a single-ported serial memory device. An innovative concept which utilizes any defective chips free from power failures has made possible a high-yield wafer-scale memory. The wafer includes an array of chips which have a DRAM (dynamic RAM) core and additional control logic known as the configuration logic (Conlog). Each Conlog is connected to its four neighbors by signal lines, which form logic networks on the wafer. An external controller transmits commands to each Conlog element to set up links between chips and configure a single contiguous data path known as a spiral. The spiral is configured on completion of wafer processing by external control software which implements chip test and linking of chips as a single-shaped data-flow chain. The DRAM core and Conlog are designed using a standard 1-Mb DRAM fabricated by the 1.3- mu m CMOS process. The waveform of the internal clock and output of the DRAM are shown as well as the output waveform of the receive terminal of Conlog.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114297062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A 1/3" format image sensor with refractory metal light shield for color video applications 一种1/3”格式的图像传感器，带有耐火金属遮光罩，适用于彩色视频应用

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48194

D. Losee, J. C. Cassidy, M. Mehra, E. Nelson, B. Burkey, G. Geisbuesch, G. Hawkins, R. Khosla, J. P. Lavine, W. Mccolgin, E. A. Trabka, A.K. Weiss

引用次数: 14

An ISDN echo-cancelling transceiver chip for 2B1Q coded U-interface 用于2B1Q编码u接口的ISDN回波消除收发器芯片

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48280

Y. Takahashi, M. Takahara, T. Makabe, D. Inami, M. Ohno, F. Nakagawa, T. Koyama, A. Kanemasa, M. Chatani, R. Ikeda

引用次数: 8

A 50 MHz 24 b floating-point DSP 一个50mhz 24b浮点DSP

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48226

Y. Shimazu, T. Kengaku, T. Fujiyama, E. Teraoka, T. Ohno, T. Tokuda, O. Tomisawa, S. Tsujimichi

引用次数: 8

A self calibration technique for monolithic high-resolution D/A converters 单片高分辨率D/A转换器的自校准技术

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48217

D. Groeneveld, H. Schouwenaars, H. Termeer, C. Bastiaansen

引用次数: 215

A 30 MIPS VLSI CPU 30 MIPS vlsi CPU

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48191

B.D. Boschma, D.M. Burns, R. Chin, N.S. Fiduccia, C. Hu, M.J. Reed, T.I. Rueth, F.X. Schumacher, V. Shen

引用次数: 11

A 16 MBPS adapter chip for the token-ring local area network 用于令牌环局域网的16 MBPS适配器芯片

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48239

J. D. Blair, A. Correale, C. Cranford, D. A. Dombrowski, C.F. Erdelyi, C. R. Hoffman, J. L. Lamphere, K. W. Lang, J.K. Lee, M. Mullen, R.R. Norman, S.F. Oakland

引用次数: 2

A mixed analog-digital secondary channel FSK modem 混合模拟-数字副通道FSK调制解调器

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48284

C. Chen, E. Huang, B. White

引用次数: 0

An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size 一个8 ns BiCMOS 1 Mb ECL SRAM，具有可配置的存储器阵列大小

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48223

H. Tran, K. Fung, D. Bell, R. Chapman, M. Harward, T. Suzuki, R. Havemann, R. Eklund, R. Fleck, D. Le, C. Wei, N. Iyengar, M. Rodder, R. Haken, D. Scott

引用次数: 22