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IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers最新文献

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A BiCMOS channelless masterslice with on-chip voltage converter 带片上电压转换器的BiCMOS无通道母片
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48248
H. Fukuda, S. Horiguchi, M. Urano, K. Fukami, K. Matsuda, N. Ohwada, H. Akiya
{"title":"A BiCMOS channelless masterslice with on-chip voltage converter","authors":"H. Fukuda, S. Horiguchi, M. Urano, K. Fukami, K. Matsuda, N. Ohwada, H. Akiya","doi":"10.1109/ISSCC.1989.48248","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48248","url":null,"abstract":"An approach to solving reliability problems due to voltage tolerance in submicron devices is described which involves lowering the operating voltage using an on-chip voltage conversion system. The masterslice has an on-chip voltage converter, TLL-compatible I/O circuits and uses advanced 0.8- mu m BiCMOS technology. A cross-sectional view of the BiCMOS device, which consists of CMOS transistors with simple n-well structure and an n-p-n bipolar transistor, is shown. The masterslice has been applied to a digital signal processing circuit. The chip contains 20 k gates, including four multiplier macrocells and random logic circuits. In the random logic circuits, which consist of double-size transistors, the packing density is 240 gate/mm/sup 2/, and the average delay is 600 ps for a two-input NAND gate with FO=3 and 1-mm wiring length. In the multipliers, 660 gate/mm/sup 2/ packing density and 450 ps average delay for 2-input NAND gate with FO=3 are attained.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128169484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 40 MHz 64-bit floating-point co-processor 一个40兆赫64位浮点协处理器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48228
K. Molnar, C.-Y. Ho, D. Staver, B. Davis, R. Jerdonek
{"title":"A 40 MHz 64-bit floating-point co-processor","authors":"K. Molnar, C.-Y. Ho, D. Staver, B. Davis, R. Jerdonek","doi":"10.1109/ISSCC.1989.48228","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48228","url":null,"abstract":"An arithmetic coprocessor capable of executing 64-bit double-precision floating-point, 32-bit single-precision floating-point, and 32-bit integer instructions has been integrated onto a 1.0-cm*1.1-cm chip in a 1.2- mu m, single-poly, double-metal bulk CMOS process. The chip contains 17000 transistors and includes a register file, two accumulators, and separate interface, multiplication, and addition subprocessors. The coprocessor which is the arithmetic unit for a multichip microprocessor system, is packaged in a 132-pin leadless ceramic chip carrier. The coprocessor can be issued a new instruction each 25-ns clock cycle, and 64-bit double-precision arithmetic with full IEEE rounding is executed at a peak rate of 26.7 MFLOPs (million floating-point operations per second). The waveforms of a store instruction operating at 40 MHz are shown.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126564468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 1,000,000 transistor microprocessor 一个100万晶体管微处理器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48231
L. Kohn, S. Fu
{"title":"A 1,000,000 transistor microprocessor","authors":"L. Kohn, S. Fu","doi":"10.1109/ISSCC.1989.48231","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48231","url":null,"abstract":"The authors describe a 1,000,000-transistor single-chip microprocessor which uses RISC (reduced-instruction-set-computer) design techniques, parallel instruction execution, a 64-bit data bus, and supercomputer architectural concepts. To achieve balanced performance, one-third of the chip area is devoted to integer instructions, including a 32-bit integer core, paging unit, and bus unit; one-third is devoted to floating-point instructions, including the floating-point control unit, add and multiply units, and a 3-D graphics unit; and one-third to three instruction and data caches. The integer unit and floating-point add and multiply units can execute in parallel to provide up to three operations per clock. Bringing the instruction and data caches on-chip allows an aggregate data rate of 1.2 Gbytes/s, which is necessary to support the parallel execution. At 50 MHz, the device achieves 105000 dhrystones and 21 MFLOPs (million floating-point operations per second) in the double-precision Linpack inner loop. The chip size is 10 mm*15 mm using a 1- mu m double-metal CHMOS process.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126574775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
A 70 MHz 32 b microprocessor with 1.0 mu m BiCMOS macrocell library 一个70 MHz 32b微处理器，带有1.0 μ m BiCMOS macrocell库
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1989.48205
T. Hotta, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi
{"title":"A 70 MHz 32 b microprocessor with 1.0 mu m BiCMOS macrocell library","authors":"T. Hotta, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi","doi":"10.1109/ISSCC.1989.48205","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48205","url":null,"abstract":"A 70-MHz, 32-b microprocessor fabricated using BiCMOS macrocells is described. The chip contains about 529 k transistors, 521 k MOS transistors (98.5%), and 8 k bipolar transistors (1.5%). This small number of bipolar transistors increases the speed of the microprocessor chip to 70 MHz (40 MHz worst case), without increasing chip size. The macrocell design strategy is to increase integration density by using CMOS-based macrocells, reduce interchip communications, and accelerate the critical path by using bipolar drivers and sense circuits without increasing the total chip size. The BiCMOS device characteristics and chip specifications are given along with the macrocell specifications.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133433384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 200 MHz CMOS phase-locked loop with dual phase detectors 一个200兆赫CMOS锁相环与双相位检测器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1989.48255
K. M. Ware, H. Lee, C. Sodini
{"title":"A 200 MHz CMOS phase-locked loop with dual phase detectors","authors":"K. M. Ware, H. Lee, C. Sodini","doi":"10.1109/ISSCC.1989.48255","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48255","url":null,"abstract":"The authors describe a 200-MHz PLL (phase-locked loop) in a 2- mu m CMOS technology employing an untrimmed current-controlled ring oscillator (CCO). Two phase detectors are included: a phase-frequency detector (PFD) for fast acquisition during data preamble (100% pulse density), and a mixer phase detector to lock on actual data (in the presence of missing pulses). Simulation results and experimental data using an external current source suggest that using the bandgap reference, the CCO supply sensitivity will be 4%/V and the CCO temperature coefficient will be about 500 p.p.m./ degrees C. Internal input and output waveforms in lock were measured from buffered test pads with a low-capacitance wideband buffered probe.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115200829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
1-volt operational amplifier with rail-to-rail input and output ranges 具有轨对轨输入和输出范围的1伏运算放大器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1989.48180
J. Fonderie, Marinus G. Maris, J. Huijsing
{"title":"1-volt operational amplifier with rail-to-rail input and output ranges","authors":"J. Fonderie, Marinus G. Maris, J. Huijsing","doi":"10.1109/ISSCC.1989.48180","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48180","url":null,"abstract":"A bipolar integrated operational amplifier (op amp), operating over nearly the full supply voltage range when the supply voltage is 1 V or more, has been designed with an input stage which can handle signals beyond the supply rails and an output stage which is able to operate within 10 mV of the supply rails. Characteristics of the op amp are 0.7-mV offset, 75-nV/ square root Hz noise, 450-kHz bandwidth, and 40-dB worst-case common-mode rejection ratio. The input and output stages are shown.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115517238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
An experimental 4 Mb CMOS EEPROM with a NAND structured cell 具有NAND结构单元的实验性4mb CMOS EEPROM
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/isscc.1989.48209
Y. Itoh, M. Momodomi, R. Shirota, Y. Iwata, R. Nakayama, R. Kirisawa, T. Tanaka, K. Toita, S. Inoue, F. Masuoka
{"title":"An experimental 4 Mb CMOS EEPROM with a NAND structured cell","authors":"Y. Itoh, M. Momodomi, R. Shirota, Y. Iwata, R. Nakayama, R. Kirisawa, T. Tanaka, K. Toita, S. Inoue, F. Masuoka","doi":"10.1109/isscc.1989.48209","DOIUrl":"https://doi.org/10.1109/isscc.1989.48209","url":null,"abstract":"A 5-V-only CMOS 512 K*8 EEPROM (electrically erasable and programmable read-only memory), which achieves 10/sup 4/ cycle endurance using a NAND-structured cell, is discussed. The main features are a programming technique appropriate to the NAND structured cell and a dynamic sense amplifier. The NAND structured cell arranges 8 bits in series, sandwiched between two select transistors. The first transistor ensures selectivity; the second prevents the current from passing during programming operation. The current cell has one select transistor per bit. However, the NAND structure has only two select transistors per 8 bits; therefore it has only 1/4 select transistor and 1/16 contact hole per bit. Thus, the NAND structure can realize a smaller cell area than that of the current cell. For high-speed programming, a page mode is adopted. In read operation, address transition detection circuitry is used to precharge the bit lines and reset the read control circuitry. A summary of design characteristics is presented.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128721069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 500 MHz 16*16 complex multiplier using self-aligned gate heterostructure FET technology 采用自对准栅异质结构场效应管技术的500 MHz 16*16复倍增器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1989.48269
T. Akinwande, R. Mactaggart, K. Betz, D. Grider, T. Nohava, J. Nohava, T. Lange, D. Tetzlaff, D. Arch
{"title":"A 500 MHz 16*16 complex multiplier using self-aligned gate heterostructure FET technology","authors":"T. Akinwande, R. Mactaggart, K. Betz, D. Grider, T. Nohava, J. Nohava, T. Lange, D. Tetzlaff, D. Arch","doi":"10.1109/ISSCC.1989.48269","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48269","url":null,"abstract":"The authors report a three-stage pipelined 4500-gate 16*16 complex multiplier with a multiply rate of 500 million products per second, producing a complex product which requires four multiplications and two additions every 8 ns at a power dissipation of 4.0 W. The multiplier uses a modified Booth's algorithm to reduce the number of adders in the multiplier net. The basic building block of the adders and registers is a DCFL NOR gate with a special load structure. The heterostructure active layers were grown by molecular beam epitaxy on 3-in semi-insulating LEC (liquid encapsulated Czochralski) GaAs substrates. The output of bits 1 and 5, operating in the self-test mode, is shown. The circuit was found to perform vector rotations correctly at a clock rate of 560 MHz with a power dissipation of 6.2 W and at 520 MHz with a power dissipation of 4 W. The 520-MHz clock at 4 W corresponds to 96 ps/gate and 0.89 mW/gate because the pipelined stages are limited to 20 gate delays. This performance represents a loaded delay with each gate driving an average fan-out of 2.5 and about 1000 mu m of interconnects at close to minimum spacing.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129296251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A high-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors 用AlGaAs/GaAs异质结双极晶体管实现的高速门阵列
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1989.48253
J.D. George, J. D. Harr, R. Young, G. Watanabe, C. Anderson, Y. Kwark, H. Basit, S. Fang, K. Wang, P. Asbeck, M. Chang, R. Nubling, G. Sullivan, M. McDonald, C. Honaker, T. McDermott
{"title":"A high-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors","authors":"J.D. George, J. D. Harr, R. Young, G. Watanabe, C. Anderson, Y. Kwark, H. Basit, S. Fang, K. Wang, P. Asbeck, M. Chang, R. Nubling, G. Sullivan, M. McDonald, C. Honaker, T. McDermott","doi":"10.1109/ISSCC.1989.48253","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48253","url":null,"abstract":"The authors report a gate array based on heterojunction bipolar transistors (HBTs) and using ECL/CML (emitter-coupled-logic/current-mode-logic) circuits. The transistors employed have f/sub t/ values up to 43 GHz. Frequency dividers based on gate-array macrocells have shown flip-flop toggle rates up to 7.0 GHz. A device technology and circuit approach targeted at ultrahigh speeds are used. The HBTs used are based on AlGaAs/GaAs epilayer structures grown by molecular beam epitaxy on semi-insulating GaAs substrates. The gate array has been personalized to produce a 4/8-bit data multiplexer, a 4/8-bit data demultiplexer, a seven-stage variable-modulus divider, and a phase detector. Operation up to a maximum frequency of 7.0 GHz was observed; the corresponding gate delay of the bilevel CML gates in the divider is 71 ps with an average fanout of 2.5.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125456507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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