J.D. George, J. D. Harr, R. Young, G. Watanabe, C. Anderson, Y. Kwark, H. Basit, S. Fang, K. Wang, P. Asbeck, M. Chang, R. Nubling, G. Sullivan, M. McDonald, C. Honaker, T. McDermott
{"title":"用AlGaAs/GaAs异质结双极晶体管实现的高速门阵列","authors":"J.D. George, J. D. Harr, R. Young, G. Watanabe, C. Anderson, Y. Kwark, H. Basit, S. Fang, K. Wang, P. Asbeck, M. Chang, R. Nubling, G. Sullivan, M. McDonald, C. Honaker, T. McDermott","doi":"10.1109/ISSCC.1989.48253","DOIUrl":null,"url":null,"abstract":"The authors report a gate array based on heterojunction bipolar transistors (HBTs) and using ECL/CML (emitter-coupled-logic/current-mode-logic) circuits. The transistors employed have f/sub t/ values up to 43 GHz. Frequency dividers based on gate-array macrocells have shown flip-flop toggle rates up to 7.0 GHz. A device technology and circuit approach targeted at ultrahigh speeds are used. The HBTs used are based on AlGaAs/GaAs epilayer structures grown by molecular beam epitaxy on semi-insulating GaAs substrates. The gate array has been personalized to produce a 4/8-bit data multiplexer, a 4/8-bit data demultiplexer, a seven-stage variable-modulus divider, and a phase detector. Operation up to a maximum frequency of 7.0 GHz was observed; the corresponding gate delay of the bilevel CML gates in the divider is 71 ps with an average fanout of 2.5.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"A high-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors\",\"authors\":\"J.D. George, J. D. Harr, R. Young, G. Watanabe, C. Anderson, Y. Kwark, H. Basit, S. Fang, K. Wang, P. Asbeck, M. Chang, R. Nubling, G. Sullivan, M. McDonald, C. Honaker, T. McDermott\",\"doi\":\"10.1109/ISSCC.1989.48253\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors report a gate array based on heterojunction bipolar transistors (HBTs) and using ECL/CML (emitter-coupled-logic/current-mode-logic) circuits. The transistors employed have f/sub t/ values up to 43 GHz. Frequency dividers based on gate-array macrocells have shown flip-flop toggle rates up to 7.0 GHz. A device technology and circuit approach targeted at ultrahigh speeds are used. The HBTs used are based on AlGaAs/GaAs epilayer structures grown by molecular beam epitaxy on semi-insulating GaAs substrates. The gate array has been personalized to produce a 4/8-bit data multiplexer, a 4/8-bit data demultiplexer, a seven-stage variable-modulus divider, and a phase detector. Operation up to a maximum frequency of 7.0 GHz was observed; the corresponding gate delay of the bilevel CML gates in the divider is 71 ps with an average fanout of 2.5.<<ETX>>\",\"PeriodicalId\":385838,\"journal\":{\"name\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1989.48253\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48253","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors
The authors report a gate array based on heterojunction bipolar transistors (HBTs) and using ECL/CML (emitter-coupled-logic/current-mode-logic) circuits. The transistors employed have f/sub t/ values up to 43 GHz. Frequency dividers based on gate-array macrocells have shown flip-flop toggle rates up to 7.0 GHz. A device technology and circuit approach targeted at ultrahigh speeds are used. The HBTs used are based on AlGaAs/GaAs epilayer structures grown by molecular beam epitaxy on semi-insulating GaAs substrates. The gate array has been personalized to produce a 4/8-bit data multiplexer, a 4/8-bit data demultiplexer, a seven-stage variable-modulus divider, and a phase detector. Operation up to a maximum frequency of 7.0 GHz was observed; the corresponding gate delay of the bilevel CML gates in the divider is 71 ps with an average fanout of 2.5.<>