用AlGaAs/GaAs异质结双极晶体管实现的高速门阵列

J.D. George, J. D. Harr, R. Young, G. Watanabe, C. Anderson, Y. Kwark, H. Basit, S. Fang, K. Wang, P. Asbeck, M. Chang, R. Nubling, G. Sullivan, M. McDonald, C. Honaker, T. McDermott
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引用次数: 21

摘要

作者报道了一种基于异质结双极晶体管(hbt)的门阵列,采用ECL/CML(发射体耦合逻辑/电流模式逻辑)电路。所使用的晶体管的f/sub /值高达43 GHz。基于门阵列宏单元的分频器显示出高达7.0 GHz的触发器切换速率。采用了以超高速为目标的器件技术和电路方法。所使用的HBTs是基于在半绝缘GaAs衬底上通过分子束外延生长的AlGaAs/GaAs薄膜结构。门阵列已经个性化,可以产生一个4/8位数据复用器、一个4/8位数据解复用器、一个七级变模分频器和一个鉴相器。观察到最高工作频率达7.0 GHz;分频器中双电平CML门对应的门延迟为71 ps,平均扇出为2.5。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A high-speed gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors
The authors report a gate array based on heterojunction bipolar transistors (HBTs) and using ECL/CML (emitter-coupled-logic/current-mode-logic) circuits. The transistors employed have f/sub t/ values up to 43 GHz. Frequency dividers based on gate-array macrocells have shown flip-flop toggle rates up to 7.0 GHz. A device technology and circuit approach targeted at ultrahigh speeds are used. The HBTs used are based on AlGaAs/GaAs epilayer structures grown by molecular beam epitaxy on semi-insulating GaAs substrates. The gate array has been personalized to produce a 4/8-bit data multiplexer, a 4/8-bit data demultiplexer, a seven-stage variable-modulus divider, and a phase detector. Operation up to a maximum frequency of 7.0 GHz was observed; the corresponding gate delay of the bilevel CML gates in the divider is 71 ps with an average fanout of 2.5.<>
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