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A 50 ns video signal processor 50ns视频信号处理器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-12-01 DOI: 10.1109/ISSCC.1989.48245
S. Nakagawa, H. Terane, T. Matsumura, H. Segawa, M. Yoshimoto, H. Shinohara, S. Kato, A. Maeda, Y. Horiba, H. Ohira, Y. Katoh, M. Iwatsuki, K. Tabuchi
{"title":"A 50 ns video signal processor","authors":"S. Nakagawa, H. Terane, T. Matsumura, H. Segawa, M. Yoshimoto, H. Shinohara, S. Kato, A. Maeda, Y. Horiba, H. Ohira, Y. Katoh, M. Iwatsuki, K. Tabuchi","doi":"10.1109/ISSCC.1989.48245","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48245","url":null,"abstract":"A 50-ns CMOS DSP (digital signal processor) with enhanced parallel architecture suited for video signal processing is reported. It has significant performance advantages, especially for video codecs in ISDN (integrated services digital network) video communication, is based on a 24-b fixed-point architecture, and operates in a five-stage pipeline (instruction-fetch, instruction-decode, source-data-transfer, execution, and destination-data-transfer). It contains 538 k transistors and typically consumes 1.4 W at an instruction cycle rate of 50 ns. The DSP was fabricated in a 1.0- mu m double-metal CMOS technology. Computation speed for the several coding procedures is approximately 3 to 10 times faster than that of traditional DSPs. A 64-kb/s video codec can be implemented with four or five DSPs for full common-source-interface-formats (CSIF) mode and one or two DSPs for 1/4 CSIF mode.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134234643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 4 b Josephson data processor chip a4b约瑟夫森数据处理器芯片
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-10-01 DOI: 10.1109/ISSCC.1989.48270
Y. Hatano, H. Mori, H. Yamada, H. Nagaishi, H. Nakane, M. Hirano, U. Kawabe
{"title":"A 4 b Josephson data processor chip","authors":"Y. Hatano, H. Mori, H. Yamada, H. Nagaishi, H. Nakane, M. Hirano, U. Kawabe","doi":"10.1109/ISSCC.1989.48270","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48270","url":null,"abstract":"The authors describe a 4-bit Josephson data processor chip featuring on-chip control and data paths and near-GHz capability. It is a closed, stand-alone chip comprising a 4-bit data path and a control path and is aimed at high-speed digital signal processing. The die is 0.5 mm square, including pads, is fabricated using 2.5- mu m-rule Nb/AlO/sub x//Nb technology, and consists of 8454 Josephson junctions and 9027 resistors. The cross-shaped junction structure realizes critical current scattering of +or-6%, and a junction characteristic voltage V/sub m/ of 50 mV. A block diagram of the Josephson data processor is shown.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128982876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 50 k-gate ECL array with substrate power supply 采用衬底供电的50k栅极ECL阵列
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-10-01 DOI: 10.1109/ISSCC.1989.48251
N. Miyoshi, M. Yoshida, K. Suzuki, M. Kokado, M. Takaoka, H. Harada
{"title":"A 50 k-gate ECL array with substrate power supply","authors":"N. Miyoshi, M. Yoshida, K. Suzuki, M. Kokado, M. Takaoka, H. Harada","doi":"10.1109/ISSCC.1989.48251","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48251","url":null,"abstract":"In microprocessor and system LSIs having several tens of thousands of gates, performance is determined by interconnection delay rather than by intrinsic gate delay because of limitations on total power consumption. This difficulty can be overcome if bipolar circuits can be made with density comparable to that of MOS circuits. To this end a bipolar technique using five interconnection layers is applied to an ECL (emitter-coupled-logic) gate array containing 53912 equivalent gates on a 7.8-mm*8.2-mm chip. The gate density is 843 gates/mm/sup 2/ for the chip and 1159 gates/mm for the internal cell region. The density results in short interconnections which reduces line delay, the major factor affecting VLSI performance. An emitter-base self-aligned structure with polysilicon electrodes and resistors (ESPER) combined with U-groove isolation with thick field oxide is employed in the device. Chip parameters and circuit schematics are presented.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131602642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The conception and evolution of digital audio 数字音频的概念和演变
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48232
H. Nakajima
{"title":"The conception and evolution of digital audio","authors":"H. Nakajima","doi":"10.1109/ISSCC.1989.48232","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48232","url":null,"abstract":"Past trends and future projections concerning the evolution of compact disks are reviewed. It is emphasized that the rapid evolution of such systems depends on the coordinated development of various new technologies, including system architectures, algorithms, components, media, and software, Of major importance was innovation in the semiconductor technology. The practical availability of such semiconductor devices as durable laser diodes, high-precision AD (analog/digital) and DA (digital/analog) converters, sophisticated logic LSIs, and high-capacity memories was indispensable for the new digital system to be realized. Related technologies that have been developed and applied since the compact disk system demonstrated the practical advantages of digital audio are reviewed. Future developments are forecast.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115375200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A realtime image processing chip set 一种实时图像处理芯片组
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48242
G. Eberhard, H. Groeneveld, O. Schneider, P. Simons
{"title":"A realtime image processing chip set","authors":"G. Eberhard, H. Groeneveld, O. Schneider, P. Simons","doi":"10.1109/ISSCC.1989.48242","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48242","url":null,"abstract":"A chip set is described which meets the requirements of calculation-intensive image processing algorithm (e.g. correlation) for real-time execution. It calculates one million two-dimensional correlation coefficients per second on a 16*16 pixel image at 25 MHz with a 6-b input resolution. The set consists of two chips, a multiplier-accumulator unit (MAC) and an arithmetic processing unit (APU). The MAC processes image data of different formats, up to 32 by 32 pixels, with a 6- or 12-b resolution, and outputs sums of products in an 18- or 36-b integer format. The APU converts these sums to a single-precision floating-point format (the internal data format) and calculates the correlation coefficient in 1- mu s with floating-point precision using the standard formula. A system configuration with both chips, a host processor, and input/output components is shown. The chip characteristics are summarized, and chip micrographs are shown.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115180834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A GPS receiver with synthesized local oscillator 一种具有合成本振的GPS接收机
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48256
R.M. Herman, C. Mason, H.P. Warren, R. A. Meier
{"title":"A GPS receiver with synthesized local oscillator","authors":"R.M. Herman, C. Mason, H.P. Warren, R. A. Meier","doi":"10.1109/ISSCC.1989.48256","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48256","url":null,"abstract":"The authors describe an IC design that includes on one chip the RF amplifier, mixer, IF amplifier, VCO (voltage-controlled oscillator), frequency divider, phase/frequency detector, *2 frequency multiplier, and power regulation functions for a Global Positioning System (GPS) receiver. The GPS L-band frequency is amplified and then downconverted to an IF near 60 MHz. A common-emitter amplifier is designed for low noise, stable gain, and a 50- Omega input match. A four-quadrant mixer is used for the downconversion, and the IF amplifier drives a 50- Omega output. The receiver chip downconverts the low-level GPS signals with conversion gain of about 50 dB while processing high-level digital signals. The total downconversion gain was measured to be greater than 45 dB. Low phase noise in the GPS signal is required for the receiver system; measured phase noise at the IF output is about -60 dBc at 10 Hz-from the carrier.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122680853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM 一个3.5 ns, 500 mW 16 kb BiCMOS ECL RAM
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48221
M. Suzuki, S. Tachibana, A. Watanabe, S. Shukuri, H. Higuchi, T. Nagano, K. Shimohigashi
{"title":"A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM","authors":"M. Suzuki, S. Tachibana, A. Watanabe, S. Shukuri, H. Higuchi, T. Nagano, K. Shimohigashi","doi":"10.1109/ISSCC.1989.48221","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48221","url":null,"abstract":"A 16-Kb RAM was designed and fabricated using a 0.5- mu m BiCMOS technology. It has a typical address access time of 3.5 ns. The RAM operates at a supply voltage of -4.5 V and features 500-mW power dissipation. A description is given of two techniques crucial to high-speed, low-power design: a wired -OR precoder combined with a low-power, high-speed level converter circuit and a direct column-sensing circuit with a cascode differential amplifier.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129099208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array 一个512 kb/5 ns BiCMOS RAM与1 kG/150 ps逻辑门阵列
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48219
M. Odaka, K. Nakamura, K. Eno, K. Ogiue, O. Saito, T. Ikeda, M. Hirao, H. Higuchi
{"title":"A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array","authors":"M. Odaka, K. Nakamura, K. Eno, K. Ogiue, O. Saito, T. Ikeda, M. Hirao, H. Higuchi","doi":"10.1109/ISSCC.1989.48219","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48219","url":null,"abstract":"An ECL (emitter-coupled-logic) 512-kb BiCMOS SRAM (statistic random access memory) with 1-kG logic and using 0.8- mu m high-performance bipolar CMOS (Hi-BiCMOS) technology is described. The RAM has 5-ns address access time and 2-ns write-pulse width. The logic gate has 150-ps propagation delay with 4-mW power dissipation. A RAM-with-logic configuration is adopted to eliminate interconnection delay between the RAM and peripheral logic and to facilitate a wide-bit RAM. The design rule dependence of the delay time of a three-input ECL OR/NOR gate and a two-input BiCMOS NAND gate is shown. On-chip address access times, under 5 ns from address latches to data-out latches at room temperature with a marching test pattern, are also shown. Major characteristics of the LSI are presented.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126411435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A CMOS 40 MHz 8 b 105 mW two-step ADC CMOS 40 MHz 8 b 105 mW两步ADC
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48213
N. Fukushima, T. Yamada, N. Kumazawa, Y. Hasegawa, M. Soneda
{"title":"A CMOS 40 MHz 8 b 105 mW two-step ADC","authors":"N. Fukushima, T. Yamada, N. Kumazawa, Y. Hasegawa, M. Soneda","doi":"10.1109/ISSCC.1989.48213","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48213","url":null,"abstract":"To meet the demand for digital signal processing of wideband video signals, a 40-MHz, 8-b ADC (analog/digital converter) with 105-mW power consumption on a 4.88-mm/sup 2/ chip has been developed using a 1.4- mu m standard-cell CMOS process. To obtain 8-b fast conversion, the ADC uses a sample-and-hold comparator with an averaging feature for differential linearity for high-speed sampling and high-frequency inputs and an expanded fine comparison to increase conversion speed. The block diagram of the converter is shown together with two techniques employed to increase conversion speed. The DC linearity of the converter at a 40-MHz conversion rate is shown. The limit of differential linearity is less than +or-0.5 least significant bit for 8 b. The measured power consumption as a function of sampling frequency and supply voltage is also shown. For 40-MHz sampled at a supply voltage of 5 V, the power consumed is 105 mW. For 14.3-MHz sampling at 3.5 V, the consumption drop to 27 mW.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126564516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
A 50 MHz uniformly pipelined 64 b floating-point arithmetic processor 一个50mhz均匀流水线64b浮点算术处理器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48229
B. Benschneider, W. Bowhill, E. Cooper, M. Gavrielov, P. Gronowski, V. Maheshwari, V. Peng, J. Pickholtz, S. Samudrala
{"title":"A 50 MHz uniformly pipelined 64 b floating-point arithmetic processor","authors":"B. Benschneider, W. Bowhill, E. Cooper, M. Gavrielov, P. Gronowski, V. Maheshwari, V. Peng, J. Pickholtz, S. Samudrala","doi":"10.1109/ISSCC.1989.48229","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48229","url":null,"abstract":"A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating-point operations and integer multiplication as defined by a superminicomputer architecture standard. The chip is composed of an interface section and a five-segment execution core. The core insists of a divider, bypassed in all instruction except division, and four fully pipelined stages that are uniformly utilized in the execution of all instructions. The performance is summarized. First pass silicon has been functionally verified at 50 MHz with a set of over one million vectors.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130868341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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