A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48221

M. Suzuki, S. Tachibana, A. Watanabe, S. Shukuri, H. Higuchi, T. Nagano, K. Shimohigashi

引用次数: 33

Abstract

A 16-Kb RAM was designed and fabricated using a 0.5- mu m BiCMOS technology. It has a typical address access time of 3.5 ns. The RAM operates at a supply voltage of -4.5 V and features 500-mW power dissipation. A description is given of two techniques crucial to high-speed, low-power design: a wired -OR precoder combined with a low-power, high-speed level converter circuit and a direct column-sensing circuit with a cascode differential amplifier.<>

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一个3.5 ns, 500 mW 16 kb BiCMOS ECL RAM

采用0.5 μ m的BiCMOS技术设计并制作了一个16kb的RAM。它的典型地址访问时间为3.5 ns。RAM工作在-4.5 V的电源电压下，功耗为500 mw。介绍了高速、低功耗设计的两种关键技术:结合低功耗、高速电平转换电路的有线或预编码器和带级联差分放大器的直接列感测电路。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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