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IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers最新文献

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A 76 MHz programmable logic sequencer 一个76兆赫可编程逻辑序列器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48202
C. Sung, P. Sasaki, R. Leung, Y. Chu, K. Le, G. Conner, R. Lane, J. de Jong, R. Cline
{"title":"A 76 MHz programmable logic sequencer","authors":"C. Sung, P. Sasaki, R. Leung, Y. Chu, K. Le, G. Conner, R. Lane, J. de Jong, R. Cline","doi":"10.1109/ISSCC.1989.48202","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48202","url":null,"abstract":"The authors describe a BiCMOS programmable logic sequencer which provides reduced power, has functional density and flexibility similar to that of CMOS, and maintains speed as high as that of bipolar devices. The device is organized as 16 inputs, 48 product terms, and 8 registered outputs. Both logic AND and OR arrays are designed for user-programmability, enabling any chosen product term to be shared as a common sum-of-products by all of the outputs without resorting to a large number of product terms. A separate BiCMOS programming path test chip, compatible with this device, was manufactured simultaneously and evaluated separately. The equivalent gate count for this device is approximately 1000 gates. A maximum operating frequency of 76 Mhz, with 6-ns clock to output delay and 7-ns input setup time at a power dissipation of 370 mW, has been achieved. The process used to fabricate this device is a merged bipolar and CMOS technology featuring 1.9- mu m L/sub eff/ and 1.2- mu m*3- mu m emitter, three-layer metal and single-layer polycide for interconnections, TiW fuses, PtSi Schottky diodes, and polysilicon resistors.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117098888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A digitally-controlled 20 b dynamic range BiCMOS stereo audio processor 一个数字控制的20b动态范围BiCMOS立体声音频处理器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48257
P. Nuijten, K. Hart
{"title":"A digitally-controlled 20 b dynamic range BiCMOS stereo audio processor","authors":"P. Nuijten, K. Hart","doi":"10.1109/ISSCC.1989.48257","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48257","url":null,"abstract":"The authors describe a stereo audio processor chip with analog performance that is achieved by a tradeoff among several important requirements including distortion, noise, DC offsets and crosstalk. In the system, each source selector has seven audio inputs and three buffered outputs. A fourth source selector output is connected to a programmable volume controller with an amplification range between +23 dB and -79 dB in 1-dB steps. The I/sup 2/C transceiver provides communication with a microcontroller by means of a two-wire serial bus. The decoder stores and decodes the received control data and drives the switches in the analog blocks. The digital part also contains a power-on-reset and power-dip control. The system architecture is determined by the low distortion target. The chip's performance is summarized in a table.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129355408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A CMOS sea-of-gates array with continuous track allocation 具有连续航迹分配的CMOS栅极海阵列
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48250
M. Okabe, Y. Okuno, T. Arakawa, I. Tomioka, T. Ohno, T. Noda, M. Hatanaka, Y. Kuramitsu
{"title":"A CMOS sea-of-gates array with continuous track allocation","authors":"M. Okabe, Y. Okuno, T. Arakawa, I. Tomioka, T. Ohno, T. Noda, M. Hatanaka, Y. Kuramitsu","doi":"10.1109/ISSCC.1989.48250","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48250","url":null,"abstract":"A macrocell architecture which is suitable for sea-of-gates (SOG) arrays and improves gate density is described. A layout scheme using a novel structure called column macrocell (CMC) implements every macrocell by stacking BCs (basic cells) along the BC column until enough gates are accumulated. In the CMC structure, the first-level wiring runs along the BC column, and the wiring channel width can be adjusted by 1-2 tracks. Therefore just as many tracks as are necessary in a channel are produced by first-level wiring. The effectiveness of the CMC structure is verified by implementing an SOG chip using LDD (lightly doped drain) PMOS and NMOS transistors with 0.8- mu m physical and 0.55- mu m effective gate length. The features of the CMC structure are compared with those of the RMC (row macrocell) structure.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130551417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A BiCMOS logic gate with positive feedback 具有正反馈的BiCMOS逻辑门
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48201
Y. Nishio, F. Murabayashi, S. Kotoku, A. Watanabe, S. Shukuri, K. Shimohigashi
{"title":"A BiCMOS logic gate with positive feedback","authors":"Y. Nishio, F. Murabayashi, S. Kotoku, A. Watanabe, S. Shukuri, K. Shimohigashi","doi":"10.1109/ISSCC.1989.48201","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48201","url":null,"abstract":"It is noted that, as BiCMOS process technology is refined, the supply voltage must be reduced due to the lower endurance voltage of the devices and the larger power dissipation of the LSI chips. As the MOS drain current decreases with supply voltage, the base current from the MOS in a BiCMOS logic gate should then be sufficient for high-speed switching. Also, as the threshold voltage of the MOS becomes lower, a full logic swing function is necessary, even for BiCMOS gates, to ensure that a DC current does not flow in the next gate. These problems were solved with a BiCMOS logic gate with positive feedback, which was fabricated using a 0.5- mu m BiCMOS device and applied to a channelless gate array for a high-speed processor. Characteristics of the proposed logic gates are summarized. Experimental t/sub pd/ and P/sub d/ versus C/sub L/ characteristics for the three-input NAND at 4-V supply voltage are shown.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125523569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
2B1Q transceiver for the ISDN subscriber loop 用于ISDN用户环路的2B1Q收发器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48281
R. Koch, R. Niggebaum, D. Vogel
{"title":"2B1Q transceiver for the ISDN subscriber loop","authors":"R. Koch, R. Niggebaum, D. Vogel","doi":"10.1109/ISSCC.1989.48281","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48281","url":null,"abstract":"A transceiver chip set for the ISDN (integrated services digital network) digital subscriber loop using quaternary code (2B1Q) is described which features full-duplex transmission with 144-kb/s net bit rate using the hybrid-balancing principle together with digital adaptive echo cancellation. The two-chip set provides the physical interface between the network termination and the digital exchange according to the T1D1 layer 1 specification for the ISDN basic access interface. A serial multiplexed standard interface allows connection to circuits supporting the layer 2 protocol control at the exchange side of the standard S-bus at the NT. Chip characteristics are listed, and block diagrams are presented.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121405868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An abuttable CCD imager for visible and X-ray focal plane arrays 可用于可见光和x射线焦平面阵列的CCD成像仪
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48196
B. Burke, R. Mountain, D. Harrison, J. Reinold, C. Doherty, G. Ricker, M. Bautz, J. Doty
{"title":"An abuttable CCD imager for visible and X-ray focal plane arrays","authors":"B. Burke, R. Mountain, D. Harrison, J. Reinold, C. Doherty, G. Ricker, M. Bautz, J. Doty","doi":"10.1109/ISSCC.1989.48196","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48196","url":null,"abstract":"Large multichip arrays for close-abutted CCDs (charged-coupled devices) are needed for surveillance applications in the visible band and for X-ray astronomy missions such as the Advanced X-ray Astrophysics Facility and the ASTRO-D satellite. A 420*420 pixel frame-transfer CCD imager which is designed to be abutted to other imagers on three sides so that arrays of 2*N chips can be constructed has been developed. A three-phase, triple-poly, buried-channel process is used, and the die size is 12 mm*20 mm. The arrays provide low-noise readout circuitry and high charge-transfer efficiency at low charge levels, critical requirements for both of the above applications. The device has also been shown to be suitable as a soft X-ray imager operating in a spectroscopic mode.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116666966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 112
A 20 ns 1 Mb CMOS burst mode EPROM 一个20 ns 1 Mb CMOS突发模式EPROM
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48225
B. Ashmore, J. Schreck, P. Truong, T. Coffman, M. Andrews
{"title":"A 20 ns 1 Mb CMOS burst mode EPROM","authors":"B. Ashmore, J. Schreck, P. Truong, T. Coffman, M. Andrews","doi":"10.1109/ISSCC.1989.48225","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48225","url":null,"abstract":"A 64-K*16-b burst-mode EPROM (electrically programmable read-only memory) with a 20-ns statistical access time was achieved using 1.4- mu m lithography. An orthogonal x-drive and split array architecture allows efficient array segmentation utilizing a contactless buried diffusion memory cell. The resultant die size is 54.6 mm/sup 2/. The contactless, buried-diffusion memory cell is constructed using a self-aligned thick oxide (SATO) process which minimizes the array dimensions by requiring diffusion contacts only every 16 bits. The SATO array can be continuously biased without a power penalty because of its virtual ground array configuration. In many system applications, the burst mode memory configuration offers performance approaching maximum processor capability.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121380820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A GaAs MESFET macrocell array 一种GaAs MESFET宏单元阵列
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48254
M. Ino, M. Togashi, S. Horiguchi, M. Hirayama, H. Kataoka
{"title":"A GaAs MESFET macrocell array","authors":"M. Ino, M. Togashi, S. Horiguchi, M. Hirayama, H. Kataoka","doi":"10.1109/ISSCC.1989.48254","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48254","url":null,"abstract":"An ultra-high-speed GaAs macrocell array is described which uses a three-level series-gate low-power source-coupled FET logic (LSCFL) as a basic circuit and a 0.4- mu m-gate flat-gate self-aligned implantation for n/sup +/-layer technology-2 (FG-SAINT-2) as a fabrication technology. The chip consists of 50 macrocells and is the equivalent of 250 gates. A typical propagation delay of unloaded ring oscillators and a typical toggle frequency of 1/4 frequency dividers fabricated on the macrocell array are 30 ps and 7.5 GHz, respectively. The basic cell is composed of three-level series gate LSCFL using all-differential signals; this circuit has twice the speed of a single-ended SCFL because it involves only one-half logic swing with the same noise margin. To verify the LSI performance, a 2*2 asynchronous transfer mode (ATM) switch element (150 equivalent gates) was fabricated on the macrocell array. The measured waveforms of the switch at 2 Gb/s are shown. The equivalent critical path gate number of the chip is 10 between flip-flops; therefore an average gate delay time of 50 ps is obtained.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125611176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 10 GHz operational amplifier in GaAs MESFET technology GaAs MESFET技术中的10ghz运算放大器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48184
L. Larson, C. Chou, D. Deakin, W. Hooper, J. Jensen, M. Thompson, M. Delaney, L. McCray, S. Rosenbaum, D. Pierson
{"title":"A 10 GHz operational amplifier in GaAs MESFET technology","authors":"L. Larson, C. Chou, D. Deakin, W. Hooper, J. Jensen, M. Thompson, M. Delaney, L. McCray, S. Rosenbaum, D. Pierson","doi":"10.1109/ISSCC.1989.48184","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48184","url":null,"abstract":"Previous implementations of high-performance op amps in GaAs technology have been hindered by low transistor g/sub m/r/sub ds/, light sensitivity, and excessive backgating, which have limited gain and bandwidth. These limitations are overcome in the circuit reported here by the use of improved processing technologies and circuit design approaches. The GaAs MESFET depletion-mode n-channel technology employs 0.2- mu m e-beam defined gates, air-bridge interconnects for low capacitance, and molecular beam epitaxy (MBE) to grow the channel layers. The average threshold voltage of the resulting FETs is -0.6 V, and the extrinsic transconductance is approximately 500 mS/mm. H/sub 21/ measurements on individual devices yield an extrapolated f/sub T/ of approximately 8 GHz. The small-signal equivalent circuit model of a 50- mu m-wide device, derived from the measured S-parameters, is shown, and the resulting element values are presented.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117088475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An 8 ns 1 Mb ECL BiCMOS SRAM 一个8n1mb ECL双mos SRAM
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48224
M. Matsui, H. Momose, Y. Urakawa, T. Maeda, A. Suzuki, N. Urakawa, K. Sato, K. Makita, J. Matsunaga, K. Ochii
{"title":"An 8 ns 1 Mb ECL BiCMOS SRAM","authors":"M. Matsui, H. Momose, Y. Urakawa, T. Maeda, A. Suzuki, N. Urakawa, K. Sato, K. Makita, J. Matsunaga, K. Ochii","doi":"10.1109/ISSCC.1989.48224","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48224","url":null,"abstract":"A description is given of a 1-Mb*1ECL (emitter-coupled-logic) SRAM (static random access memory) fabricated with a 0.8- mu m BiCMOS technology which has 8-ns access time and is 10K-I/O (input/output) compatible. To achieve sub-10 ns address access time and low power consumption, an ECL CMOS level converter, a bit-line peripheral circuit, and an automatic power saving function are employed. Details of the 0.8- mu m BiCMOS process technology are summarized, and an oscilloscope photograph shows 8-ns address access time under nominal conditions. The RAM characteristics are summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115865128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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