A 76 MHz programmable logic sequencer

C. Sung, P. Sasaki, R. Leung, Y. Chu, K. Le, G. Conner, R. Lane, J. de Jong, R. Cline
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引用次数: 3

Abstract

The authors describe a BiCMOS programmable logic sequencer which provides reduced power, has functional density and flexibility similar to that of CMOS, and maintains speed as high as that of bipolar devices. The device is organized as 16 inputs, 48 product terms, and 8 registered outputs. Both logic AND and OR arrays are designed for user-programmability, enabling any chosen product term to be shared as a common sum-of-products by all of the outputs without resorting to a large number of product terms. A separate BiCMOS programming path test chip, compatible with this device, was manufactured simultaneously and evaluated separately. The equivalent gate count for this device is approximately 1000 gates. A maximum operating frequency of 76 Mhz, with 6-ns clock to output delay and 7-ns input setup time at a power dissipation of 370 mW, has been achieved. The process used to fabricate this device is a merged bipolar and CMOS technology featuring 1.9- mu m L/sub eff/ and 1.2- mu m*3- mu m emitter, three-layer metal and single-layer polycide for interconnections, TiW fuses, PtSi Schottky diodes, and polysilicon resistors.<>
一个76兆赫可编程逻辑序列器
作者描述了一种BiCMOS可编程逻辑序列器,它具有与CMOS相似的功能密度和灵活性,并且具有与双极器件一样高的速度。该设备组织为16个输入,48个产品项和8个注册输出。逻辑与和或数组都是为用户可编程性而设计的,允许任何选择的产品项作为所有输出的公共产品和共享,而无需诉诸大量的产品项。同时制作了与该器件兼容的单独BiCMOS编程路径测试芯片,并分别进行了评估。该器件的等效门数约为1000个门。最大工作频率为76 Mhz,时钟输出延迟为6 ns,输入设置时间为7 ns,功耗为370 mW。用于制造该器件的工艺是双极和CMOS技术的融合,具有1.9 μ m L/sub /和1.2 μ m*3 μ m发射极,用于互连的三层金属和单层多晶硅,TiW熔断器,PtSi肖特基二极管和多晶硅电阻。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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