M. Matsui, H. Momose, Y. Urakawa, T. Maeda, A. Suzuki, N. Urakawa, K. Sato, K. Makita, J. Matsunaga, K. Ochii
{"title":"An 8 ns 1 Mb ECL BiCMOS SRAM","authors":"M. Matsui, H. Momose, Y. Urakawa, T. Maeda, A. Suzuki, N. Urakawa, K. Sato, K. Makita, J. Matsunaga, K. Ochii","doi":"10.1109/ISSCC.1989.48224","DOIUrl":null,"url":null,"abstract":"A description is given of a 1-Mb*1ECL (emitter-coupled-logic) SRAM (static random access memory) fabricated with a 0.8- mu m BiCMOS technology which has 8-ns access time and is 10K-I/O (input/output) compatible. To achieve sub-10 ns address access time and low power consumption, an ECL CMOS level converter, a bit-line peripheral circuit, and an automatic power saving function are employed. Details of the 0.8- mu m BiCMOS process technology are summarized, and an oscilloscope photograph shows 8-ns address access time under nominal conditions. The RAM characteristics are summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48224","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
A description is given of a 1-Mb*1ECL (emitter-coupled-logic) SRAM (static random access memory) fabricated with a 0.8- mu m BiCMOS technology which has 8-ns access time and is 10K-I/O (input/output) compatible. To achieve sub-10 ns address access time and low power consumption, an ECL CMOS level converter, a bit-line peripheral circuit, and an automatic power saving function are employed. Details of the 0.8- mu m BiCMOS process technology are summarized, and an oscilloscope photograph shows 8-ns address access time under nominal conditions. The RAM characteristics are summarized.<>