IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers最新文献_第3页

A 45 ns 16 Mb DRAM with triple-well structure 45 ns 16mb三孔结构DRAM

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48276

S. Fujii, M. Ogihara, M. Shimizu, M. Yoshida, K. Numata, T. Hara, S. Watanabe, S. Sawada, T. Mizuno, J. Kumagai, S. Yoshikawa, S. Kaki, Y. Saito, H. Aochi, T. Hamamoto, K. Toita

引用次数: 52

An acoustic echo canceler 回声消除器

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48283

W. Hsu, F. Chui, D. Hodges

引用次数: 11

A rate adaption coprocessor for terminal adapters with U-interface modems 一种速率适应协处理器，用于带u接口调制解调器的终端适配器

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48238

D.H. Rabaey, H.J. Busschaert, P. Reusens, L.M. Verpooten

{"title":"A rate adaption coprocessor for terminal adapters with U-interface modems","authors":"D.H. Rabaey, H.J. Busschaert, P. Reusens, L.M. Verpooten","doi":"10.1109/ISSCC.1989.48238","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48238","url":null,"abstract":"A rate adapter is described which provides a compact cost- and power-efficient means of connecting any data terminal by means of the integrated services digital network (ISDN). In contrast to previous solutions, this chip supports both single and multichannel applications. In single-channel applications, the rate adapter chip and an 8-bit microcontroller with RAM and ROM implement a complete system. In multichannel applications, up to 256 rate adapters can connect to one PCM (pulse-code modulation) highway without any additional hardware. Statistical subchannel multiplexing compliant with CCITT recommendations G.704 and I.460 is easily realized owing to the integrated programmable bus adapter and a flexible bandwidth assignment. The rate adapter was designed in a 2- mu m double-metal CMOS technology. The 50 k-transistor device dissipates 80 mW in worst-case conditions. The rate adapter chip is a key building block in a 144-kb/s U-modem. Connecting rate adapters in parallel to a single-chip U-interface circuit allows the time-division multiplexing of up to 16 data terminals onto one full-duplex two-wire 155-kb/s link. As a result, this system provides a low-cost access to the ISDN for existing terminal equipment.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115809829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An integrated 150 Vpp, 12 kV/ mu s class AB CRT-driving amplifier 集成150 Vpp, 12 kV/ mu级AB级crt驱动放大器

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48262

P. Blanke, J. Verdaasdonk

{"title":"An integrated 150 Vpp, 12 kV/ mu s class AB CRT-driving amplifier","authors":"P. Blanke, J. Verdaasdonk","doi":"10.1109/ISSCC.1989.48262","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48262","url":null,"abstract":"An integrated output amplifier with an output voltage swing of more than 150 V/sub pp/, a slew rate of 12 kV/ mu s, a large-signal bandwidth of 30 MHz, and a small-signal bandwidth exceeding 60 MHz is described. It is intended to drive the cathode of a cathode ray tube (CRT) in a projection television or a high-definition television (HDTV) set. The amplifier comprises a transadmittance stage followed by a feedback transimpedance amplifier. A zero in the feedback transfer allows the open-loop voltage gain of the transimpedance amplifier to have a -12-dB/octave slope at the unity loop-gain frequency. A zero in the transfer of the transadmittance stage results in a larger overall bandwidth than is possible in a conventional voltage-feedback configuration. The high-voltage DMOS technology which is used is based on a 10-mask bipolar process with double-sided p+ isolation and n+ collector diffusions. The 150-V/sub pp/ step response is shown. The rise and fall times are 11 and 12 ns, respectively, yielding slew rates of 13 and 12 kV/ mu s respectively. The overshoot is 12%. The small-signal (10 V/sub pp/) bandwidth, limited by the third pole of the transimpedance amplifier, exceeds 60 MHz. The large-signal (150-V/sub pp/) bandwidth, limited by slew rate, is 30 MHz.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116334276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Si bipolar 15 GHz static frequency divider and 10 Gb/s multiplexer 一个硅双极15ghz静态分频器和10gb /s多路复用器

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48264

P. Wegner, L. Treitinger, A. Wieder, H. Rein

引用次数: 11

Frame interline transfer CCD sensor for HDTV camera 用于高清摄像机的帧间传输CCD传感器

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48193

T. Nobusada, M. Azuma, H. Toyoda, T. Kuroda, K. Horii, T. Otsuki, G. Kano

引用次数: 14

A 1.5 V DRAM for battery-based applications 1.5 V DRAM，用于电池应用

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48271

M. Aoki, J. Etoh, K. Itoh, S. Kimura, Y. Kawamoto

引用次数: 34

A 23 ps/2.1 mW ECL gate 23ps /2.1 mW ECL栅极

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48265

K. Toh, C. Chuang, T. Chen, J. Warnock, G. Li, K. Chin, T. Ning

引用次数: 16

Merged CMOS/bipolar current switch logic 合并CMOS/双极电流开关逻辑

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48199

W. Heimsch, B. Hoffmann, R. Krebs, E. Muellner, B. Pfaeffel, K. Ziemann

引用次数: 16

A 64 b RISC microprocessor for a parallel computer system 用于并行计算机系统的64b RISC微处理器

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48186

K. Kaneko, T. Okamoto, M. Nakajima, Y. Nakakura, S. Gokita, J. Nishikawa, Yuji Tanikawa, H. Kadota

{"title":"A 64 b RISC microprocessor for a parallel computer system","authors":"K. Kaneko, T. Okamoto, M. Nakajima, Y. Nakakura, S. Gokita, J. Nishikawa, Yuji Tanikawa, H. Kadota","doi":"10.1109/ISSCC.1989.48186","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48186","url":null,"abstract":"A description is given of a microprocessor that is designed as a processing element (PE) of a parallel computer system, executing a 64-b floating-point ADD/SUB/MULT in 50 ns and a DIV in 350 ns because of its pipelined structure and dedicated floating-point blocks. The processor employs RISC (reduced-instruction-set-computer) architecture and executes most of its 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology and contains 440 K transistors in a 14.4*13.5-mm/sup 2/ die. The processor provides high-speed double-precision floating-point operation, high reliability in data handling, communication capability between PEs and the host controller device, and hardware support for efficient code generation by the compiler. The maximum performance of the processor is 20 MFLOPS (million floating-point operations per second) or 20 MIPS (million instructions per second). Typical performance is 4 MFLOPS, measured during execution of Gaussian elimination operation. The major characteristics and performance of the processor are summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133277563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4