23ps /2.1 mW ECL栅极

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48265

K. Toh, C. Chuang, T. Chen, J. Warnock, G. Li, K. Chin, T. Ning

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引用次数: 16

摘要

模拟输出波形在0.1,0.3和0.6 pf负载的设计优化为0.3- pf标称负载显示。描述了一种交流耦合APD ECL(有源下拉发射器耦合逻辑)门，该门在低功率(1-2 mW)状态下具有显著改善的门延迟。在2.1和1.1 mw /栅极功率下，空载栅极延迟分别为23和35 ps，采用双极技术，采用双聚自校准工艺，发射极宽度为0.8 μ m(掩模)。器件的横截面与用于环形振荡器的基本栅极的SEM(扫描电子显微镜)显微照片一起呈现。

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A 23 ps/2.1 mW ECL gate

Simulated output waveforms at 0.1, 0.3 and, 0.6-pF loading of a design optimized for a 0.3-pF nominal load are shown. An AC-coupled APD ECL (active-pull-down emitter-coupled-logic) gate with significantly improved gate delay in the low-power (1-2 mW) regime is described. Unloaded gate delays of 23 and 35 ps at 2.1 and 1.1-mW/gate power, respectively, were demonstrated in a bipolar technology using a double-poly, self-aligned process with emitter width of 0.8 mu m (mask). The device cross-section is presented along with an SEM (scanning electron microscopy) micrograph of the basic gate used in the ring oscillator.<>

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来源期刊

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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