一种速率适应协处理器,用于带u接口调制解调器的终端适配器

D.H. Rabaey, H.J. Busschaert, P. Reusens, L.M. Verpooten
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引用次数: 2

摘要

本文描述了一种速率适配器,它提供了一种紧凑、经济、节能的方式,可以通过综合业务数字网(ISDN)连接任何数据终端。与以前的解决方案相比,该芯片支持单通道和多通道应用。在单通道应用中,速率适配器芯片和带有RAM和ROM的8位微控制器实现了一个完整的系统。在多通道应用中,多达256个速率适配器可以连接到一个PCM(脉冲码调制)高速公路,而无需任何额外的硬件。由于集成的可编程总线适配器和灵活的带宽分配,符合CCITT建议G.704和I.460的统计子信道复用很容易实现。速率适配器采用2 μ m双金属CMOS技术设计。50k晶体管器件在最坏情况下耗散80mw。速率适配器芯片是144kb /s u -调制解调器的关键组成部分。将速率适配器与单芯片u接口电路并行连接,允许多达16个数据终端在一条全双工双线155kb /s链路上进行时分多路复用。因此,该系统为现有终端设备提供了一种低成本的ISDN接入方式。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A rate adaption coprocessor for terminal adapters with U-interface modems
A rate adapter is described which provides a compact cost- and power-efficient means of connecting any data terminal by means of the integrated services digital network (ISDN). In contrast to previous solutions, this chip supports both single and multichannel applications. In single-channel applications, the rate adapter chip and an 8-bit microcontroller with RAM and ROM implement a complete system. In multichannel applications, up to 256 rate adapters can connect to one PCM (pulse-code modulation) highway without any additional hardware. Statistical subchannel multiplexing compliant with CCITT recommendations G.704 and I.460 is easily realized owing to the integrated programmable bus adapter and a flexible bandwidth assignment. The rate adapter was designed in a 2- mu m double-metal CMOS technology. The 50 k-transistor device dissipates 80 mW in worst-case conditions. The rate adapter chip is a key building block in a 144-kb/s U-modem. Connecting rate adapters in parallel to a single-chip U-interface circuit allows the time-division multiplexing of up to 16 data terminals onto one full-duplex two-wire 155-kb/s link. As a result, this system provides a low-cost access to the ISDN for existing terminal equipment.<>
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