A 64 b RISC microprocessor for a parallel computer system

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48186

K. Kaneko, T. Okamoto, M. Nakajima, Y. Nakakura, S. Gokita, J. Nishikawa, Yuji Tanikawa, H. Kadota

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引用次数: 4

Abstract

A description is given of a microprocessor that is designed as a processing element (PE) of a parallel computer system, executing a 64-b floating-point ADD/SUB/MULT in 50 ns and a DIV in 350 ns because of its pipelined structure and dedicated floating-point blocks. The processor employs RISC (reduced-instruction-set-computer) architecture and executes most of its 47 instructions in one 50-ns cycle. The chip is fabricated in 1.2- mu m n-well CMOS technology and contains 440 K transistors in a 14.4*13.5-mm/sup 2/ die. The processor provides high-speed double-precision floating-point operation, high reliability in data handling, communication capability between PEs and the host controller device, and hardware support for efficient code generation by the compiler. The maximum performance of the processor is 20 MFLOPS (million floating-point operations per second) or 20 MIPS (million instructions per second). Typical performance is 4 MFLOPS, measured during execution of Gaussian elimination operation. The major characteristics and performance of the processor are summarized.<>

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用于并行计算机系统的64b RISC微处理器

描述了一种被设计成并行计算机系统的处理单元(PE)的微处理器，由于其流水线结构和专用浮点块，它在50 ns内执行64-b浮点ADD/SUB/MULT，在350 ns内执行DIV。该处理器采用精简指令集计算机(RISC)架构，其47条指令中的大部分在一个50-ns周期内执行。该芯片采用1.2 μ m n阱CMOS技术制造，在14.4*13.5 mm/sup 2/芯片中包含440 K晶体管。该处理器提供高速双精度浮点运算，数据处理的高可靠性，pe与主控制器设备之间的通信能力，以及编译器对高效代码生成的硬件支持。处理器的最大性能是20 MFLOPS(每秒百万个浮点操作)或20 MIPS(每秒百万条指令)。典型的性能是4 MFLOPS，在执行高斯消去操作期间测量。总结了该处理器的主要特点和性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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