1.5 V DRAM，用于电池应用

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48271

M. Aoki, J. Etoh, K. Itoh, S. Kimura, Y. Kawamoto

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引用次数: 34

摘要

作者报告了低功耗，高信噪比(SNR) 16 Mbit DRAM(动态RAM)技术，该技术允许1.5 v电池工作。为了降低功耗，数据线电压摆幅是感应放大器中nMOS和pMOS晶体管的阈值电压之和。采用板脉冲电路技术、三电平字脉冲和3.4 μ m/sup /数据线屏蔽STC单元提高了存储阵列的信噪比。将DRAM的主要特性与SNB(存储节点增强)技术和传统的半v /sub CC/电路技术进行了比较。

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A 1.5 V DRAM for battery-based applications

The authors report low-power, high-signal-to-noise-ratio (SNR) 16 Mbit DRAM (dynamic RAM) techniques which allow 1.5-V battery operation. To reduce power consumption, the data-line voltage swing is the sum of the threshold voltages for nMOS and pMOS transistors in the sense amplifier. A plate-pulse circuit technique, a three-level word pulse, and a 3.4- mu m/sup 2/ data-line shielded STC cell enhance SNR in the memory array. The main features of the DRAM are compared with those of the SNB (storage-node-boosted) technique and a conventional half-V/sub CC/ circuit technique.<>

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来源期刊

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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