A 1.5 V DRAM for battery-based applications

Abstract

The authors report low-power, high-signal-to-noise-ratio (SNR) 16 Mbit DRAM (dynamic RAM) techniques which allow 1.5-V battery operation. To reduce power consumption, the data-line voltage swing is the sum of the threshold voltages for nMOS and pMOS transistors in the sense amplifier. A plate-pulse circuit technique, a three-level word pulse, and a 3.4- mu m/sup 2/ data-line shielded STC cell enhance SNR in the memory array. The main features of the DRAM are compared with those of the SNB (storage-node-boosted) technique and a conventional half-V/sub CC/ circuit technique.<>