D.H. Rabaey, H.J. Busschaert, P. Reusens, L.M. Verpooten
{"title":"A rate adaption coprocessor for terminal adapters with U-interface modems","authors":"D.H. Rabaey, H.J. Busschaert, P. Reusens, L.M. Verpooten","doi":"10.1109/ISSCC.1989.48238","DOIUrl":null,"url":null,"abstract":"A rate adapter is described which provides a compact cost- and power-efficient means of connecting any data terminal by means of the integrated services digital network (ISDN). In contrast to previous solutions, this chip supports both single and multichannel applications. In single-channel applications, the rate adapter chip and an 8-bit microcontroller with RAM and ROM implement a complete system. In multichannel applications, up to 256 rate adapters can connect to one PCM (pulse-code modulation) highway without any additional hardware. Statistical subchannel multiplexing compliant with CCITT recommendations G.704 and I.460 is easily realized owing to the integrated programmable bus adapter and a flexible bandwidth assignment. The rate adapter was designed in a 2- mu m double-metal CMOS technology. The 50 k-transistor device dissipates 80 mW in worst-case conditions. The rate adapter chip is a key building block in a 144-kb/s U-modem. Connecting rate adapters in parallel to a single-chip U-interface circuit allows the time-division multiplexing of up to 16 data terminals onto one full-duplex two-wire 155-kb/s link. As a result, this system provides a low-cost access to the ISDN for existing terminal equipment.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48238","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A rate adapter is described which provides a compact cost- and power-efficient means of connecting any data terminal by means of the integrated services digital network (ISDN). In contrast to previous solutions, this chip supports both single and multichannel applications. In single-channel applications, the rate adapter chip and an 8-bit microcontroller with RAM and ROM implement a complete system. In multichannel applications, up to 256 rate adapters can connect to one PCM (pulse-code modulation) highway without any additional hardware. Statistical subchannel multiplexing compliant with CCITT recommendations G.704 and I.460 is easily realized owing to the integrated programmable bus adapter and a flexible bandwidth assignment. The rate adapter was designed in a 2- mu m double-metal CMOS technology. The 50 k-transistor device dissipates 80 mW in worst-case conditions. The rate adapter chip is a key building block in a 144-kb/s U-modem. Connecting rate adapters in parallel to a single-chip U-interface circuit allows the time-division multiplexing of up to 16 data terminals onto one full-duplex two-wire 155-kb/s link. As a result, this system provides a low-cost access to the ISDN for existing terminal equipment.<>