45 ns 16mb三孔结构DRAM

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48276

S. Fujii, M. Ogihara, M. Shimizu, M. Yoshida, K. Numata, T. Hara, S. Watanabe, S. Sawada, T. Mizuno, J. Kumagai, S. Yoshikawa, S. Kaki, Y. Saito, H. Aochi, T. Hamamoto, K. Toita

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引用次数: 52

摘要

作者描述了一种采用三孔CMOS技术制造的16mb DRAM(动态RAM)，可以实现最佳的井偏置选择。利用该技术，实现了优化的芯片架构和p通道负载字行引导驱动程序，该驱动程序结合了45 ns行访问频闪访问时间的前身。该存储单元采用四分之一音调排列，并结合了交叉位线/共享感测放大器方案。这克服了在按比例缩小的沟槽或埋式堆叠电容器电池中定义电容器极板聚的困难。所示为RAM的输出波形。总结了16M DRAM的特点。它能够快速页面，静态列，或蚕食操作和-*1或*4位的组织，由选择绑定配置决定。

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A 45 ns 16 Mb DRAM with triple-well structure

The authors describe a 16-Mb DRAM (dynamic RAM) fabricated with a triple-well CMOS technology that enables optimum choice of well bias. With this technology, an optimized chip architecture, and a p-channel load word-line bootstrap driver incorporating a predecoder a 45-ns row-access-strobe access time is achieved. The memory cell is in a quarter-pitched arrangement combined with an interdigitated bit-line/shared-sense-amplifier scheme. This overcomes the difficulty of defining capacitor-plate poly in a scaled-down trench or buried-stacked-capacitor cell. The output waveform of the RAM is shown. The features of the 16M DRAM are summarized. It is capable of fast page, static column, or nibble operation and -*1- or *4-bit organization, determined by the choice of bonding configuration.<>

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来源期刊

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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