B. Ashmore, J. Schreck, P. Truong, T. Coffman, M. Andrews
{"title":"一个20 ns 1 Mb CMOS突发模式EPROM","authors":"B. Ashmore, J. Schreck, P. Truong, T. Coffman, M. Andrews","doi":"10.1109/ISSCC.1989.48225","DOIUrl":null,"url":null,"abstract":"A 64-K*16-b burst-mode EPROM (electrically programmable read-only memory) with a 20-ns statistical access time was achieved using 1.4- mu m lithography. An orthogonal x-drive and split array architecture allows efficient array segmentation utilizing a contactless buried diffusion memory cell. The resultant die size is 54.6 mm/sup 2/. The contactless, buried-diffusion memory cell is constructed using a self-aligned thick oxide (SATO) process which minimizes the array dimensions by requiring diffusion contacts only every 16 bits. The SATO array can be continuously biased without a power penalty because of its virtual ground array configuration. In many system applications, the burst mode memory configuration offers performance approaching maximum processor capability.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 20 ns 1 Mb CMOS burst mode EPROM\",\"authors\":\"B. Ashmore, J. Schreck, P. Truong, T. Coffman, M. Andrews\",\"doi\":\"10.1109/ISSCC.1989.48225\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 64-K*16-b burst-mode EPROM (electrically programmable read-only memory) with a 20-ns statistical access time was achieved using 1.4- mu m lithography. An orthogonal x-drive and split array architecture allows efficient array segmentation utilizing a contactless buried diffusion memory cell. The resultant die size is 54.6 mm/sup 2/. The contactless, buried-diffusion memory cell is constructed using a self-aligned thick oxide (SATO) process which minimizes the array dimensions by requiring diffusion contacts only every 16 bits. The SATO array can be continuously biased without a power penalty because of its virtual ground array configuration. In many system applications, the burst mode memory configuration offers performance approaching maximum processor capability.<<ETX>>\",\"PeriodicalId\":385838,\"journal\":{\"name\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-02-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1989.48225\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48225","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 64-K*16-b burst-mode EPROM (electrically programmable read-only memory) with a 20-ns statistical access time was achieved using 1.4- mu m lithography. An orthogonal x-drive and split array architecture allows efficient array segmentation utilizing a contactless buried diffusion memory cell. The resultant die size is 54.6 mm/sup 2/. The contactless, buried-diffusion memory cell is constructed using a self-aligned thick oxide (SATO) process which minimizes the array dimensions by requiring diffusion contacts only every 16 bits. The SATO array can be continuously biased without a power penalty because of its virtual ground array configuration. In many system applications, the burst mode memory configuration offers performance approaching maximum processor capability.<>