用于ISDN用户环路的2B1Q收发器

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48281

R. Koch, R. Niggebaum, D. Vogel

{"title":"用于ISDN用户环路的2B1Q收发器","authors":"R. Koch, R. Niggebaum, D. Vogel","doi":"10.1109/ISSCC.1989.48281","DOIUrl":null,"url":null,"abstract":"A transceiver chip set for the ISDN (integrated services digital network) digital subscriber loop using quaternary code (2B1Q) is described which features full-duplex transmission with 144-kb/s net bit rate using the hybrid-balancing principle together with digital adaptive echo cancellation. The two-chip set provides the physical interface between the network termination and the digital exchange according to the T1D1 layer 1 specification for the ISDN basic access interface. A serial multiplexed standard interface allows connection to circuits supporting the layer 2 protocol control at the exchange side of the standard S-bus at the NT. Chip characteristics are listed, and block diagrams are presented.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"2B1Q transceiver for the ISDN subscriber loop\",\"authors\":\"R. Koch, R. Niggebaum, D. Vogel\",\"doi\":\"10.1109/ISSCC.1989.48281\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A transceiver chip set for the ISDN (integrated services digital network) digital subscriber loop using quaternary code (2B1Q) is described which features full-duplex transmission with 144-kb/s net bit rate using the hybrid-balancing principle together with digital adaptive echo cancellation. The two-chip set provides the physical interface between the network termination and the digital exchange according to the T1D1 layer 1 specification for the ISDN basic access interface. A serial multiplexed standard interface allows connection to circuits supporting the layer 2 protocol control at the exchange side of the standard S-bus at the NT. Chip characteristics are listed, and block diagrams are presented.<<ETX>>\",\"PeriodicalId\":385838,\"journal\":{\"name\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"volume\":\"2016 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-02-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1989.48281\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48281","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

描述了一种采用四元码(2B1Q)的ISDN(综合业务数字网)数字用户环路的收发器芯片组，该芯片组采用混合平衡原理和数字自适应回波抵消，具有144-kb/s净比特率的全双工传输特点。双芯片组按照ISDN基本接入接口T1D1层1规范，提供网络终端与数字交换机之间的物理接口。串行多路复用标准接口允许连接到支持NT标准s总线交换端的第2层协议控制的电路。列出了芯片特性，并给出了框图。

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2B1Q transceiver for the ISDN subscriber loop

A transceiver chip set for the ISDN (integrated services digital network) digital subscriber loop using quaternary code (2B1Q) is described which features full-duplex transmission with 144-kb/s net bit rate using the hybrid-balancing principle together with digital adaptive echo cancellation. The two-chip set provides the physical interface between the network termination and the digital exchange according to the T1D1 layer 1 specification for the ISDN basic access interface. A serial multiplexed standard interface allows connection to circuits supporting the layer 2 protocol control at the exchange side of the standard S-bus at the NT. Chip characteristics are listed, and block diagrams are presented.<>

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IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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