T. Hotta, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi
{"title":"一个70 MHz 32b微处理器,带有1.0 μ m BiCMOS macrocell库","authors":"T. Hotta, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi","doi":"10.1109/ISSCC.1989.48205","DOIUrl":null,"url":null,"abstract":"A 70-MHz, 32-b microprocessor fabricated using BiCMOS macrocells is described. The chip contains about 529 k transistors, 521 k MOS transistors (98.5%), and 8 k bipolar transistors (1.5%). This small number of bipolar transistors increases the speed of the microprocessor chip to 70 MHz (40 MHz worst case), without increasing chip size. The macrocell design strategy is to increase integration density by using CMOS-based macrocells, reduce interchip communications, and accelerate the critical path by using bipolar drivers and sense circuits without increasing the total chip size. The BiCMOS device characteristics and chip specifications are given along with the macrocell specifications.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 70 MHz 32 b microprocessor with 1.0 mu m BiCMOS macrocell library\",\"authors\":\"T. Hotta, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi\",\"doi\":\"10.1109/ISSCC.1989.48205\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 70-MHz, 32-b microprocessor fabricated using BiCMOS macrocells is described. The chip contains about 529 k transistors, 521 k MOS transistors (98.5%), and 8 k bipolar transistors (1.5%). This small number of bipolar transistors increases the speed of the microprocessor chip to 70 MHz (40 MHz worst case), without increasing chip size. The macrocell design strategy is to increase integration density by using CMOS-based macrocells, reduce interchip communications, and accelerate the critical path by using bipolar drivers and sense circuits without increasing the total chip size. The BiCMOS device characteristics and chip specifications are given along with the macrocell specifications.<<ETX>>\",\"PeriodicalId\":385838,\"journal\":{\"name\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1989.48205\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48205","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 70 MHz 32 b microprocessor with 1.0 mu m BiCMOS macrocell library
A 70-MHz, 32-b microprocessor fabricated using BiCMOS macrocells is described. The chip contains about 529 k transistors, 521 k MOS transistors (98.5%), and 8 k bipolar transistors (1.5%). This small number of bipolar transistors increases the speed of the microprocessor chip to 70 MHz (40 MHz worst case), without increasing chip size. The macrocell design strategy is to increase integration density by using CMOS-based macrocells, reduce interchip communications, and accelerate the critical path by using bipolar drivers and sense circuits without increasing the total chip size. The BiCMOS device characteristics and chip specifications are given along with the macrocell specifications.<>