一个70 MHz 32b微处理器,带有1.0 μ m BiCMOS macrocell库

T. Hotta, T. Bandoh, A. Hotta, T. Nakano, S. Iwamoto, S. Adachi
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引用次数: 0

摘要

介绍了一种采用BiCMOS宏单元制备的70 mhz 32b微处理器。该芯片包含约529k晶体管、521k MOS晶体管(98.5%)和8k双极晶体管(1.5%)。这少量的双极晶体管将微处理器芯片的速度提高到70兆赫(最坏的情况是40兆赫),而不增加芯片尺寸。宏单元的设计策略是通过使用基于cmos的宏单元来提高集成密度,减少片间通信,并通过使用双极驱动器和感测电路来加速关键路径,而不增加芯片的总尺寸。给出了BiCMOS器件特性和芯片规格,并给出了macrocell规格
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 70 MHz 32 b microprocessor with 1.0 mu m BiCMOS macrocell library
A 70-MHz, 32-b microprocessor fabricated using BiCMOS macrocells is described. The chip contains about 529 k transistors, 521 k MOS transistors (98.5%), and 8 k bipolar transistors (1.5%). This small number of bipolar transistors increases the speed of the microprocessor chip to 70 MHz (40 MHz worst case), without increasing chip size. The macrocell design strategy is to increase integration density by using CMOS-based macrocells, reduce interchip communications, and accelerate the critical path by using bipolar drivers and sense circuits without increasing the total chip size. The BiCMOS device characteristics and chip specifications are given along with the macrocell specifications.<>
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