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IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers最新文献

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A 16 Mb/s data detector and timing recovery circuit for token ring LAN 用于令牌环局域网的16mb /s数据检测器和定时恢复电路
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48237
J. Scott, R. Starke, R. Ramachandran, D. Pietruszynki, S. Bell, K. McClellan, K. Thompson
{"title":"A 16 Mb/s data detector and timing recovery circuit for token ring LAN","authors":"J. Scott, R. Starke, R. Ramachandran, D. Pietruszynki, S. Bell, K. McClellan, K. Thompson","doi":"10.1109/ISSCC.1989.48237","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48237","url":null,"abstract":"A 1.75- mu m CMOS interface circuit for a differential Manchester-coded 16-Mb/s token-ring local area network (LAN) is presented. The chip provides fixed gain and slicing functions as well as integrated clock recovery, data timing, and lock detection. When it is used in tandem with a digital controller/driver chip, a complete 16-Mb IEEE 802.5-1988 standard-compatible token-ring transceiver is realized. Block-level functionality of the interface circuit is discussed, following by more detailed subcircuit descriptions and a presentation of measured results. The measured jitter transfer function of the PLL phase-locked to a high-transition-density data stream is shown.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127687351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 16 Mb mask ROM with programmable redundancy 具有可编程冗余的16mb掩码ROM
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48206
Y. Naruke, T. Iwase, M. Takizawa, K. Saito, M. Asano, H. Nishimura, T. Mochizuki
{"title":"A 16 Mb mask ROM with programmable redundancy","authors":"Y. Naruke, T. Iwase, M. Takizawa, K. Saito, M. Asano, H. Nishimura, T. Mochizuki","doi":"10.1109/ISSCC.1989.48206","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48206","url":null,"abstract":"In response to demands for a mask ROM with large bit capacity, a 1M-word*16 bit mask ROM with 120-ns access time has been fabricated. A programmable redundancy technique utilizes electrically fusible polysilicon links with the secondary breakdown mechanism of a MOSFET for high production yield and small chip area. The memory cell matrix arranged in 8192 rows*2048 columns and is divided into four blocks by two sets of row decoders in order to reduce word line delay. The redundancy cell array is composed of 8 rows*256 columns which can replace four defective quarter-rows. The mask ROM is fabricated in single-polysilicon single-aluminium twin-well CMOS technology with 0.7- mu m photolithography for high bit density. The process parameters and design features of the mask ROM are given together with a block diagram.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128232204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A DSP-based watthour meter 基于dsp的电能表
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48195
M. Negahban, C. Chen, B. White, M. Ouellette, W. Germer
{"title":"A DSP-based watthour meter","authors":"M. Negahban, C. Chen, B. White, M. Ouellette, W. Germer","doi":"10.1109/ISSCC.1989.48195","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48195","url":null,"abstract":"A high-accuracy, three-phase electronic watthour meter, implemented in a 3.5- mu m double-poly CMOS technology, is described. It receives inputs from voltage and current sensors, measures both real and reactive power, and outputs pulses whose rate is proportional to energy flow. The meter is accurate to 0.3% of reading over 3.5 decades. A block diagram is presented, and the device functions are described. The DSP (digital signal processor) is developed as a macro cell with customized ROM/RAM. It has a 16-bit data path which can shift N bits and accumulate in one clock cycle. Both scalar and variable multiplications are possible.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"51 14","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132389553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A single chip BiMOS telephone set 单芯片BiMOS电话机
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48278
C. Nguyen, P. Consiglio, F. Adduci, G. Vanalli, F. Marti, M. Robbe, J. Le Corre
{"title":"A single chip BiMOS telephone set","authors":"C. Nguyen, P. Consiglio, F. Adduci, G. Vanalli, F. Marti, M. Robbe, J. Le Corre","doi":"10.1109/ISSCC.1989.48278","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48278","url":null,"abstract":"A single-chip telephone set in BCD (bipolar, CMOS and DMOS) technology is described. It integrates all of the functions usually found in a telephone set: reception, transmission, power supply generation, ringer, loudspeaker, and bistandard dialing (loop disconnect and dual-tone multifrequency). A 30-V bipolar technology is used to treat analog signals, 12-V CMOS for control and generation of the pulses/tones for dialing, and 60-V DMOS for ringer high-voltage driver. The block diagrams of the analog and digital parts are shown. The single chip has proved that a telephone set combining mixed features like high voltage, high power, low noise, and intelligibility can be integrated using a mixed BCD bipolar CMOS and process. The availability of differing components on the same substrate makes possible the solution of problems in the analog domain without compromise.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132653766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 55 ns 16 Mb DRAM 55ns 16mb DRAM
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48275
T. Takeshima, M. Takada, H. Koike, H. Watanabe, S. Koshimaru, K. Mitake, W. Kikuchi, T. Tanigawa, T. Murotani, K. Noda, K. Tasaka, K. Yamanaka, K. Koyama
{"title":"A 55 ns 16 Mb DRAM","authors":"T. Takeshima, M. Takada, H. Koike, H. Watanabe, S. Koshimaru, K. Mitake, W. Kikuchi, T. Tanigawa, T. Murotani, K. Noda, K. Tasaka, K. Yamanaka, K. Koyama","doi":"10.1109/ISSCC.1989.48275","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48275","url":null,"abstract":"The authors describe a 16-Mb CMOS DRAM (dynamic RAM) with 55-ns access time and 130-mm/sup 2/ chip area. It features a high-speed latched sensing (LS) scheme and a built-in self-test (BIST) function with a microprogrammable ROM in which automatic test pattern generation procedures are stored by microcoded programs. To achieve 55-ns access time, the DRAM combines the LS scheme with conventional double-Al-layer wiring and 5-V peripheral circuits. The bit-line sense circuits, driven at 3.3 V from an internal voltage converter to ensure 0.6 mu m MOS memory cell reliability, are shown. Both sensing speed and signal voltage are lower at 3.3 V operation than at 5 V operation. However, the LS scheme compensates for these drawbacks and achieves fast access time and high sensitivity. Operational waveforms for 55-ns row-address-strobe access time for a typical chip under normal conditions are shown, and chip characteristics are summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132321266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A CMOS to 100 K ECL interface circuit 一种CMOS与100k ECL接口电路
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48267
M. Pedersen, P. Metz
{"title":"A CMOS to 100 K ECL interface circuit","authors":"M. Pedersen, P. Metz","doi":"10.1109/ISSCC.1989.48267","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48267","url":null,"abstract":"The authors have designed and fabricated a true CMOS/ECL (emitter-coupled logic) interface in a 0.9- mu m CMOS technology. This interface requires only a single external reference resistor to be completely ECL 100 K compatible. It accepts as input AC- or DC-coupled, differential or single-ended ECL 100 K signals and outputs the same. The interface demonstrates 100-MHz single-ended and 200-MHz differential operation while maintaining true ECL output levels and is part of a monolithic 200-MHz clock recovery circuit. Interface circuit characteristics are listed, and a block diagram is presented.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134179209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A front-end processor for modems 调制解调器的前端处理器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48282
K. Yamamoto, Osamu Yanaga, Y. Okuaki
{"title":"A front-end processor for modems","authors":"K. Yamamoto, Osamu Yanaga, Y. Okuaki","doi":"10.1109/ISSCC.1989.48282","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48282","url":null,"abstract":"The authors describe the front-end processor (FEP) which permits the construction of a multistandard modem system, incorporating the CCITT V.32 echo canceling scheme, using a general-purpose signal processor. The FEP is divided into a digital signal processing (DSP) block and an analog-digital/digital-analog conversion block. The DSP is designed to handle biquad filtering, tone generation, automatic gain control, call-progress-tone detection, and carrier detection. The multiplier, ALU (arithmetic and logic unit), and RAM are adapted to handle 22-bit data operation and to obtain high resolution and a 16-bit dynamic range operation in fixed-point calculations. The measured bit error rate of 14.4-kb/s trellis coding modem using the FEP is less than 10/sup -5/ at a signal-to-noise ratio of 27 dB under the US unconditioned 3002 line. The chip is fabricated in a 1.5- mu m double-poly double-metal CMOS process and designed using an automatic layout tool.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131304787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An 80 b, 6.7 MFLOPS floating-point processor with vector/matrix instructions 一个80b, 6.7 MFLOPS的带有矢量/矩阵指令的浮点处理器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48230
T. Nakayama, S. Kojima, H. Harigai, H. Igarashi, K. Tamada, T. Toba
{"title":"An 80 b, 6.7 MFLOPS floating-point processor with vector/matrix instructions","authors":"T. Nakayama, S. Kojima, H. Harigai, H. Igarashi, K. Tamada, T. Toba","doi":"10.1109/ISSCC.1989.48230","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48230","url":null,"abstract":"A description is given of an 80-b CMOS VLSI floating-point processor (FPP) in 1.2- mu m double-metal layer CMOS which contains 433000 transistors on an 11.6-mm*14.9-mm die. It operates at 20 MHz, dissipates 1.5 W, and is assembled in a 68-lead pin-grid-array package. The FPP is designed as a coprocessor for 32-b microprocessors. It implements data formats, arithmetic rounding modes, and exception types which are defined by the IEEE 754 standard. The chip can handle single (32 b), double (64 b), and double-extended (80 b) floating-point data formats. The complex-instruction-set-computer- (CISC-) like 78-instruction set includes 22 mathematical functions such as sin, cos, arctan, exp, and log, and 24 vector/matrix operations such as add, multiply, and inner product. The features and performance of the device are summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114388882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 310 k pixel bipolar imager (BASIS) 310k像素双极成像仪(BASIS)
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48197
Nobu yoshi Tanaka, Seiji Hashimoto, Mahito Shinohara, S. Sugawa, Masakazu Morishita, Shigeyuki Matsumoto, Voshio Nakamura, Tadahiro Ohmi
{"title":"A 310 k pixel bipolar imager (BASIS)","authors":"Nobu yoshi Tanaka, Seiji Hashimoto, Mahito Shinohara, S. Sugawa, Masakazu Morishita, Shigeyuki Matsumoto, Voshio Nakamura, Tadahiro Ohmi","doi":"10.1109/ISSCC.1989.48197","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48197","url":null,"abstract":"A bipolar imager with an amplification function in each pixel has been developed using BiCMOS technology. The imager, which stores photocarriers in the base regions of the bipolar transistor pixels, is called the base-stored image sensor (BASIS). BASIS-type devices have been faced with three problems: (1) a reset transistor is needed in each pixel to initialize base voltage; (2) nonuniformity of offset voltage appears as fixed pattern noise; and (3) blooming is induced by intense light. Effective methods of dealing with these problems have been found. A BASIS imager with 310 k pixels in a 2/3-in optical format is described. The device specifications and characteristics of the imager are summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124382593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A 9 ns 1 Mb CMOS SRAM 一个9 ns 1 Mb CMOS SRAM
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48222
K. Sasaki, S. Hanamura, K. Ishibashi, T. Yamanaka, N. Hashimoto, T. Nishida, K. Shimohigashi, S. Honjo
{"title":"A 9 ns 1 Mb CMOS SRAM","authors":"K. Sasaki, S. Hanamura, K. Ishibashi, T. Yamanaka, N. Hashimoto, T. Nishida, K. Shimohigashi, S. Honjo","doi":"10.1109/ISSCC.1989.48222","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48222","url":null,"abstract":"A 1-Mb (256k*4/1M*1) CMOS SRAM (static random access memory), fabricated using a half-micron triple-poly double-metal CMOS technology, is reported. A 9-ns access time is attained with 5-V supply and 30-pF load capacitance. This access time has been achieved with a three-stage pMOS cross-coupled sense amplifier, 0.6- mu m high-performance MOSFETs, and an optimized internal supply voltage scheme. A redundancy scheme with no access time penalty has been incorporated. The sense amplifier circuit combined with a CMOS cross-coupled preamplifier has under 10-ns access time. Address and data output waveforms are shown. Typical active current is 55 mA at 30 MHz, and typical standby current is 15 mA (TTL). Typical RAM characteristics are listed.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124549262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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