A front-end processor for modems

The authors describe the front-end processor (FEP) which permits the construction of a multistandard modem system, incorporating the CCITT V.32 echo canceling scheme, using a general-purpose signal processor. The FEP is divided into a digital signal processing (DSP) block and an analog-digital/digital-analog conversion block. The DSP is designed to handle biquad filtering, tone generation, automatic gain control, call-progress-tone detection, and carrier detection. The multiplier, ALU (arithmetic and logic unit), and RAM are adapted to handle 22-bit data operation and to obtain high resolution and a 16-bit dynamic range operation in fixed-point calculations. The measured bit error rate of 14.4-kb/s trellis coding modem using the FEP is less than 10/sup -5/ at a signal-to-noise ratio of 27 dB under the US unconditioned 3002 line. The chip is fabricated in a 1.5- mu m double-poly double-metal CMOS process and designed using an automatic layout tool.<>