A 9 ns 1 Mb CMOS SRAM

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48222

K. Sasaki, S. Hanamura, K. Ishibashi, T. Yamanaka, N. Hashimoto, T. Nishida, K. Shimohigashi, S. Honjo

引用次数: 10

Abstract

A 1-Mb (256k*4/1M*1) CMOS SRAM (static random access memory), fabricated using a half-micron triple-poly double-metal CMOS technology, is reported. A 9-ns access time is attained with 5-V supply and 30-pF load capacitance. This access time has been achieved with a three-stage pMOS cross-coupled sense amplifier, 0.6- mu m high-performance MOSFETs, and an optimized internal supply voltage scheme. A redundancy scheme with no access time penalty has been incorporated. The sense amplifier circuit combined with a CMOS cross-coupled preamplifier has under 10-ns access time. Address and data output waveforms are shown. Typical active current is 55 mA at 30 MHz, and typical standby current is 15 mA (TTL). Typical RAM characteristics are listed.<>

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一个9 ns 1 Mb CMOS SRAM

报道了一种采用半微米三聚双金属CMOS技术制造的1mb (256k*4/1M*1) CMOS SRAM(静态随机存取存储器)。使用5v电源和30pf负载电容可获得9ns的访问时间。这个访问时间是通过一个三级pMOS交叉耦合感测放大器，0.6 μ m高性能mosfet和优化的内部电源电压方案来实现的。一个没有访问时间惩罚的冗余方案已被纳入。结合CMOS交叉耦合前置放大器的感测放大电路的访问时间小于10ns。显示了地址和数据输出波形。典型的工作电流为55ma在30mhz，典型的待机电流为15ma (TTL)。下面列出了典型的RAM特性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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