J. D. Blair, A. Correale, C. Cranford, D. A. Dombrowski, C.F. Erdelyi, C. R. Hoffman, J. L. Lamphere, K. W. Lang, J.K. Lee, M. Mullen, R.R. Norman, S.F. Oakland
{"title":"用于令牌环局域网的16 MBPS适配器芯片","authors":"J. D. Blair, A. Correale, C. Cranford, D. A. Dombrowski, C.F. Erdelyi, C. R. Hoffman, J. L. Lamphere, K. W. Lang, J.K. Lee, M. Mullen, R.R. Norman, S.F. Oakland","doi":"10.1109/ISSCC.1989.48239","DOIUrl":null,"url":null,"abstract":"An adaptor chip is described which is the result of a cost-reduction and function-enhancement project that yielded a single CMOS VLSI module capable of performing all major LAN (local area network) adapter functions and supporting a 16-Mb/s data rate. The chip when combined with external PROM and RAM modules, bus drivers, and discrete line interface components, forms a complete token-ring adapter. The protocol handler performs most bit- and byte-level functions required to implement the IEEE 802.5 protocol and contains rate machines which automatically perform frame-transmit and receive operations directly between the network and the adapter RAM. The design of the chip uses a mix of fully custom and standard cell approaches. Two process enhancements were employed in a standard digital process in order to achieve high-performance analog functions: a high-implant thin-oxide capacitor and a low-threshold n-channel transistor.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"15 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 16 MBPS adapter chip for the token-ring local area network\",\"authors\":\"J. D. Blair, A. Correale, C. Cranford, D. A. Dombrowski, C.F. Erdelyi, C. R. Hoffman, J. L. Lamphere, K. W. Lang, J.K. Lee, M. Mullen, R.R. Norman, S.F. Oakland\",\"doi\":\"10.1109/ISSCC.1989.48239\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An adaptor chip is described which is the result of a cost-reduction and function-enhancement project that yielded a single CMOS VLSI module capable of performing all major LAN (local area network) adapter functions and supporting a 16-Mb/s data rate. The chip when combined with external PROM and RAM modules, bus drivers, and discrete line interface components, forms a complete token-ring adapter. The protocol handler performs most bit- and byte-level functions required to implement the IEEE 802.5 protocol and contains rate machines which automatically perform frame-transmit and receive operations directly between the network and the adapter RAM. The design of the chip uses a mix of fully custom and standard cell approaches. Two process enhancements were employed in a standard digital process in order to achieve high-performance analog functions: a high-implant thin-oxide capacitor and a low-threshold n-channel transistor.<<ETX>>\",\"PeriodicalId\":385838,\"journal\":{\"name\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"volume\":\"15 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-02-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1989.48239\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48239","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 16 MBPS adapter chip for the token-ring local area network
An adaptor chip is described which is the result of a cost-reduction and function-enhancement project that yielded a single CMOS VLSI module capable of performing all major LAN (local area network) adapter functions and supporting a 16-Mb/s data rate. The chip when combined with external PROM and RAM modules, bus drivers, and discrete line interface components, forms a complete token-ring adapter. The protocol handler performs most bit- and byte-level functions required to implement the IEEE 802.5 protocol and contains rate machines which automatically perform frame-transmit and receive operations directly between the network and the adapter RAM. The design of the chip uses a mix of fully custom and standard cell approaches. Two process enhancements were employed in a standard digital process in order to achieve high-performance analog functions: a high-implant thin-oxide capacitor and a low-threshold n-channel transistor.<>