30 MIPS vlsi CPU

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48191

B.D. Boschma, D.M. Burns, R. Chin, N.S. Fiduccia, C. Hu, M.J. Reed, T.I. Rueth, F.X. Schumacher, V. Shen

{"title":"30 MIPS vlsi CPU","authors":"B.D. Boschma, D.M. Burns, R. Chin, N.S. Fiduccia, C. Hu, M.J. Reed, T.I. Rueth, F.X. Schumacher, V. Shen","doi":"10.1109/ISSCC.1989.48191","DOIUrl":null,"url":null,"abstract":"A description is given of a VLSI CPU which implements an existing 32-b architecture with a set of 140 instructions, most of which can be executed within one effective clock cycle. The device is fabricated in an nMOS process with three metal layers having minimum metal-1 line width of 1.5 mu m and drawn device lengths of 1.7 mu m. The die, containing 183000 transistors, is 1.4 cm*1.4 cm. The CPU directly addresses external SRAMs organized as a two-way set-associative split 512-kb-instruction/512-kb-data cache. Separate instruction and data paths allow for concurrent overlapped cache memory access. Chip specifications are presented, and the CPU data path is shown.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A 30 MIPS VLSI CPU\",\"authors\":\"B.D. Boschma, D.M. Burns, R. Chin, N.S. Fiduccia, C. Hu, M.J. Reed, T.I. Rueth, F.X. Schumacher, V. Shen\",\"doi\":\"10.1109/ISSCC.1989.48191\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A description is given of a VLSI CPU which implements an existing 32-b architecture with a set of 140 instructions, most of which can be executed within one effective clock cycle. The device is fabricated in an nMOS process with three metal layers having minimum metal-1 line width of 1.5 mu m and drawn device lengths of 1.7 mu m. The die, containing 183000 transistors, is 1.4 cm*1.4 cm. The CPU directly addresses external SRAMs organized as a two-way set-associative split 512-kb-instruction/512-kb-data cache. Separate instruction and data paths allow for concurrent overlapped cache memory access. Chip specifications are presented, and the CPU data path is shown.<<ETX>>\",\"PeriodicalId\":385838,\"journal\":{\"name\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"volume\":\"55 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-02-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1989.48191\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48191","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 11

摘要

描述了一种实现现有32b架构的VLSI CPU，该CPU具有140条指令，其中大部分指令可以在一个有效时钟周期内执行。该器件采用nMOS工艺制造，采用三层金属层，最小金属-1线宽度为1.5 μ m，器件长度为1.7 μ m，芯片尺寸为1.4 cm*1.4 cm，包含183000个晶体管。CPU直接寻址外部sram，组织为双向集关联分割512-kb指令/512-kb数据缓存。单独的指令和数据路径允许并发的重叠缓存存储器访问。给出了芯片规格，并给出了CPU的数据路径。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 30 MIPS VLSI CPU

A description is given of a VLSI CPU which implements an existing 32-b architecture with a set of 140 instructions, most of which can be executed within one effective clock cycle. The device is fabricated in an nMOS process with three metal layers having minimum metal-1 line width of 1.5 mu m and drawn device lengths of 1.7 mu m. The die, containing 183000 transistors, is 1.4 cm*1.4 cm. The CPU directly addresses external SRAMs organized as a two-way set-associative split 512-kb-instruction/512-kb-data cache. Separate instruction and data paths allow for concurrent overlapped cache memory access. Chip specifications are presented, and the CPU data path is shown.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

自引率

0.00%

发文量