{"title":"A reconfigurable DMOS control chip for an electronic typewriter","authors":"G. Pietrobon, D. Rossi","doi":"10.1109/ISSCC.1989.48259","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48259","url":null,"abstract":"A custom chip combining complex signal circuits and power sections is described. It provides the power subsystem for a portable typewriter, including drivers for three different loads, the associated control logic, and a switched-mode power supply (SMPS). This IC can exchange load drive and control strategy information with a standard microprocessor by means of an 8-bit common-I/O data bus. The microprocessor interface decodes the first four bits, which, depending on the content of the remaining four, are used to operate the power transistors, activate the PWM (pulse width modulation) loop, and set the D/A (digital/analog) output value. The fabrication technique used for the integrated circuit combines the DMOS process with some steps typical of the junction-isolated technique. The regulated voltage used to drive the internal circuit blocks and the external microprocessor can deliver 5 W (5 V, 1 A) with an efficiency greater than 90% at a typical frequency of 100 kHz.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122761509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Trimming analog circuits using floating-gate analog MOS memory","authors":"L. Carley","doi":"10.1109/ISSCC.1989.48260","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48260","url":null,"abstract":"The author presents an analog trim-voltage memory (ATVM) which employs a floating-gate MOS structure similar to that used in digital electrically erasable and programmable read-only memories (EEPROMs). The ATVM is suitable for trimming the offset voltages and currents resulting from threshold mismatches in analog circuits such as operational amplifiers and comparators. It can be incorporated into a standard digital CMOS process without the additional processing steps typically needed for EEPROM fabrication. This floating-gate memory uses hot-electron injection to decrease the floating-gate voltage and electron tunneling from the floating gate to increase the voltage. A possible use of the ATVM circuit is shown along with the input stage of a two-stage Miller compensated op amp.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123709608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 20 MIPS sustained 32 b CMOS microprocessor with 64 b data bus","authors":"N. Jouppi, J.Y.-F. Tang, J. Dion","doi":"10.1109/ISSCC.1989.48192","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48192","url":null,"abstract":"The authors describe a full-custom 32-b microprocessor which uses a 1.5- mu m drawn n-well CMOS technology with single polycide and two levels of metal. The die size is 7.76 mm*6.21 mm and contains 180 k transistors, of which 150 k are used in the cache or register file. The CPU executes an RISC instruction set with simple and regular encoding. The chip has been designed for operation at 20 MIPS (million instructions per second), running large benchmarks in a complete system. Power dissipation at 25 degrees C with a 5-V supply is under 3 W. The chip has 136 signal, 16 power, and 16 ground pads and is packaged in a 176-pin plastic pin-grid-array package with eight decoupling capacitors. The CPU pipeline and machine organization and the instruction fetch pipestage are shown.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114849550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 13-bit, 160 kHz, differential analog to digital converter","authors":"S. Ramet","doi":"10.1109/ISSCC.1989.48216","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48216","url":null,"abstract":"The author describes a 13-bit, 160-kHz differential ADC (analog-to-digital converter), and an 80-kHz version, both including a reference circuit delivering two voltages that are symmetrical with respect to the power supply midpoint. These circuits are implemented in the 1.2- mu m CMOS double-metal process using an extra n+ diffusion to accommodate poly/n+ capacitors. Starting from the k-bit linearity requirement for the capacitor array and considering previous results, the bits were partitioned into P=4 bits for the resistor-string and K=9 bits for the capacitor array. The fast Fourier transform (FFT) result is shown for a 5-kHz sine-wave full-scale input sampled at 160 kHz. The performance of the circuit is summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115350257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Satoh, T. Nishimura, M. Tatsuki, A. Ohba, S. Hine, K. Sakaue, Y. Kuramitsu
{"title":"A 209 k-transistor ECL gate array with RAM","authors":"H. Satoh, T. Nishimura, M. Tatsuki, A. Ohba, S. Hine, K. Sakaue, Y. Kuramitsu","doi":"10.1109/ISSCC.1989.48252","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48252","url":null,"abstract":"The authors describe a gate array with an ECL (emitter-coupled-logic) cell structure for implementing a high-density configurable RAM. A unit based on a variable size cell is modified to achieve such a RAM. Every unit has an extra transistor buried under the power bus to eliminate area penalty. One memory bit is constructed using one buried transistor plus three transistors in a unit. An n-p-n transistor and a tap resistor load cell are employed for structural matching with the logic gates. Since the read current is supplied directly from the V/sub CC/ bus instead of the word line, the transistor size of the word-line driver is minimized. The standby and read currents are 120 mu A and 800 mu A, respectively. The decoder, sense amplifiers, and word-line drivers are implemented by logic gates. RAM size can be varied by each unit row; the bit increment is 144. The process employs double-polysilicon self-aligned technology with a silicide-base electrode of TiSi/sub 2/ and triple-layer metallization. The features of the gate array are listed.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115647484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. D'Luna, K. Parulski, T.J. Kenney, R. H. Hibbard, R. Guidash, P. R. Shelley, W.A. Cook, G.W. Brown, T. Tredwell
{"title":"A digital video signal processor for color image sensors","authors":"L. D'Luna, K. Parulski, T.J. Kenney, R. H. Hibbard, R. Guidash, P. R. Shelley, W.A. Cook, G.W. Brown, T. Tredwell","doi":"10.1109/ISSCC.1989.48240","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48240","url":null,"abstract":"The authors describe signal processor (DSP) for CCD (charge-coupled-device) cameras using a specified color filter array pattern. A block diagram of the DSP chip is shown. The chip has been designed and fabricated in a 2- mu m single-poly double-metal CMOS process. Eight scan-test registers were used at selected points in the processing chain to enable the entire chip to be tested, including ROMs and line delays, with 16 k vectors. The chip is functional at a maximum clock rate of 14.3 MHz. An image processed by the device is shown. The data path is designed with simple ripple-carry adders and dynamic registers. The on-chip programmable delay lines and 14.3-MHz clock-rate allow the chip to accommodate sensors for up to 768 active pixels, making it suitable for NTSC, CCIR 601 and PAL video standards.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122646530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Cernea, G. Samachisa, C. Su, Hui-Fang Tsai, Y. Kao, C. Wang, Y.S. Chen, A. Renninger, T. Wong, J. Brennan, J. Haines
{"title":"A 1 Mb flash EEPROM","authors":"R. Cernea, G. Samachisa, C. Su, Hui-Fang Tsai, Y. Kao, C. Wang, Y.S. Chen, A. Renninger, T. Wong, J. Brennan, J. Haines","doi":"10.1109/ISSCC.1989.48211","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48211","url":null,"abstract":"A 1-Mb flash EEPROM (electrically erasable and programmable read-only memory) with a 5.6- mu m*4.4- mu m cell is fabricated with a double-polysilicon, single-metal, n-well CMOS process. A double-diffused drain structure is used to reduce hot-electron degradation of n-channel peripheral devices. The memory is organized into 1024 rows and 128 columns for each output. Erase and programming operations are internally controlled by a timer that is stabilized against temperature and voltage supply variations. Addresses and data are latched during program and erase operations. Internal pumps generate the high voltage for the erase operation. Six redundant rows and two redundant columns are provided to enhance yield. Flash EEPROM cells similar to the array cells are used as the programmable elements in the redundancy circuits. Process parameters are given.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"380 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124735103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Kikuchi, Y. Nukada, Y. Aoki, T. Kanou, Y. Endo, T. Nishitani
{"title":"A single-chip 16-bit 25 ns realtime video/image signal processor","authors":"K. Kikuchi, Y. Nukada, Y. Aoki, T. Kanou, Y. Endo, T. Nishitani","doi":"10.1109/ISSCC.1989.48246","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48246","url":null,"abstract":"A single-chip real-time video/image processor (VISP) has been developed that integrates functions based on a variable seven-stage pipeline arithmetic architecture in a 16-bit fixed-point data format. A three-input adder implemented in complementary CMOS reduced-swing logic, which is twice as fast as conventional CMOS logic, achieving a 25-ns instruction cycle, is shown. Single-VISP processing times are: edge detection (3*3 Laplacian), 14.8 ms; distance calculation, 1.7 ms; temporal filtering (1-tap IR), 5.0 ms; linear quantization, 3.3 ms; and 3/5*3/5 picture reduction (separate 5-tap FIR), 5.9 ms. An example is shown of a two-dimensional discrete cosine transformation which requires 26.3 ms to execute with one VISP when 256*256 pixel processing at a 25-ns instruction cycle is employed.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125062557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Conrad, R. Devlin, D. Dobberpuhl, B. Gieseke, R. Heye, G. Hoeppner, J. Kowaleski, M. Ladd, J. Montanaro, S. Morris, R. Stamm, H. Tumblin, R. Witek
{"title":"A 50 MIPS (peak) 32/64 b microprocessor","authors":"R. Conrad, R. Devlin, D. Dobberpuhl, B. Gieseke, R. Heye, G. Hoeppner, J. Kowaleski, M. Ladd, J. Montanaro, S. Morris, R. Stamm, H. Tumblin, R. Witek","doi":"10.1109/ISSCC.1989.48185","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48185","url":null,"abstract":"An RISC (reduced-instruction-set-computer) microprocessor is described that, subject to data dependencies, can issue one 32-b instruction every 20-ns cycle to achieve peak performance of 50 MIPS (million instructions per second) for worst-case process and operating conditions. The chip includes a 64-b by 32-b general-purpose register file, a 22-b by 32-b privileged-register file, a 1 kB eight-way-associative virtual instruction cache, a 2-kB direct-mapped write-through physical data cache, an 8-entry fully associative instruction address translation buffer, a 32-entry fully associative data address translation buffer, a 10-entry by 64-b output data FIFO, 3-entry by 64-b instruction input FIFO, a 2-entry by 64-b data input FIFO, hardware support for multiprocessing, and a heavily pipelined integer execution unit. Although the execution unit has a 32-b datapath, the data cache, external interface, and register file are organized by 64 b to maximize data transfer rates and to allow single-cache issue of all double-precision instructions. The chip is fabricated in a 1.5- mu m drawn n-well double-metal CMOS process. It contains 294353 transistors, of which 135680 are in the cache arrays, measures 14.5 mm*9.5 mm, and is mounted in a 224-pin surface-mount leaded chip carrier. Power dissipation is 9 W at a 20 ns cycle time.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124683933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 16 kb ferroelectric nonvolatile memory with a bit parallel architecture","authors":"R. Womack, Donald E Tolsch","doi":"10.1109/ISSCC.1989.48273","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48273","url":null,"abstract":"The authors describe an experimental 16-kb nonvolatile memory using two memory cells per bit with one transistor and one ferroelectric capacitor per memory cell. The RAM measures 5 mm*7 mm with 462 mu m/sup 2/ per bit. It is built in a 2- mu m CMOS n-well process and has a chip-enable access time of 200 ns. The authors also demonstrate a bit-parallel architecture in which the common plate of the capacitors runs parallel to the bit lines and connects all bits in a given column. The typical characteristics of the device are given.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121972560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}