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IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers最新文献

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A 1.4 M-transistor CMOS gate array with 4 ns RAM 1.4 m晶体管CMOS门阵列与4 ns RAM
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48249
T. Takahashi, M. Kawashima, M. Fujita, I. Kobayashi, K. Arai, T. Okabe
{"title":"A 1.4 M-transistor CMOS gate array with 4 ns RAM","authors":"T. Takahashi, M. Kawashima, M. Fujita, I. Kobayashi, K. Arai, T. Okabe","doi":"10.1109/ISSCC.1989.48249","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48249","url":null,"abstract":"A submicron CMOS gate array implemented with 0.8- mu m triple-metal-layer process technology is presented. The chip includes 1.4 M transistors which can be used as 130k logic gates, and a 38-kb SRAM (static random-access memory) and is housed in a 400-pin pin-grid array-package. Typical gate delay time is 0.35 ns, and SRAM access time is 4.0 ns. The process parameters are shown, and the basic features of the chip are listed. A memory controller for a general-purpose, 64-b CPU has been fabricated on this gate array in order to prove feasibility. Systematic placement and the equal load capacitance of the clock drivers make maximum clock skew time +or-1.0 ns within the chip.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126440362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 5 V-only 256 kbit CMOS flash EEPROM 一个5v - 256kbit CMOS闪存EEPROM
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48207
S. D'Arrigo, G. Imondi, G. Santin, M. Gill, R. Cleavelin, S. Spagliccia, E. Tomassetti, S. Lin, A. Nguyen, P. Shah, G. Savarese, D. McElroy
{"title":"A 5 V-only 256 kbit CMOS flash EEPROM","authors":"S. D'Arrigo, G. Imondi, G. Santin, M. Gill, R. Cleavelin, S. Spagliccia, E. Tomassetti, S. Lin, A. Nguyen, P. Shah, G. Savarese, D. McElroy","doi":"10.1109/ISSCC.1989.48207","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48207","url":null,"abstract":"The authors describe a 256-kbit flash EEPROM (electrically erasable and programmable read-only memory) device which requires only 5 V for program, erase, and read operations and has performance and cost comparable to that of the recently reported dual-power-supply flash EEPROMs, which require 12 V for programming and erase and 5 V for read. The memory cell consists of a floating-gate transistor and a merged-pass-gate transistor. The process is array-contactless EEPROM (ACEE), with buried source/drain for the bit lines with a tunnel oxide module and a 20-V CMOS module. The program and erase operations employ the Fowler-Nordheim current tunneled through 100-AA oxide when the proper electrical voltages are applied to the selected bit. The device and technology parameters are summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126557929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
BiCMOS current source reference network for ULSI BiCMOS with ECL circuitry 带ECL电路的ULSI BiCMOS电流源参考网络
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48203
H. Tran, P. Fung, D. Scott
{"title":"BiCMOS current source reference network for ULSI BiCMOS with ECL circuitry","authors":"H. Tran, P. Fung, D. Scott","doi":"10.1109/ISSCC.1989.48203","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48203","url":null,"abstract":"A BiCMOS current source reference network which eliminates the impact of DC power supply voltage drops on the operation of ECL (emitter coupled logic) circuits is described. This is essential for implementing ECL design techniques in ULSI BiCMOS circuits. Using the current source network, reference voltages are generated locally, so that the ECL voltage references are correctly referenced to the local power supply potentials. A power-supply-insensitive bandgap reference generator is used to generate precision on-chip voltage references and current sources. The bandgap reference circuit uses both MOS and bipolar transistors and is much simpler than a similar design using bipolar-only circuitry. The micrograph of the test chip containing the bandgap circuit nd BiCMOS op amp analog drivers is shown. The drivers are designed for multiple-reference-level regeneration. The test chip has been fabricated using a 0.8- mu m BiCMOS process. The typical characteristics of the bandgap circuit and the analog driver are shown.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128452683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A single-ended BiCMOS sense circuit for digital circuits 用于数字电路的单端BiCMOS感测电路
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48200
G. Rosseel, M. Horowitz, R. Dutton, R. Cline
{"title":"A single-ended BiCMOS sense circuit for digital circuits","authors":"G. Rosseel, M. Horowitz, R. Dutton, R. Cline","doi":"10.1109/ISSCC.1989.48200","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48200","url":null,"abstract":"The authors present a fast single-ended BiCMOS sense circuit with CMOS output levels which is noise-insensitive enough to be used in a CMOS environment. A bipolar transistor is used in common-emitter configuration. Assuming that the bipolar transistor is conducting current, yet not saturated, a small voltage swing at the base is enough to turn the transistor off, and the collector voltage rises rapidly. An analog current mirror is used to prevent the bipolar transistor from saturating while maintaining a CMOS low-output voltage and to provide noise immunity. The full implementation of the sense circuit is shown.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125099006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
500 k transistor custom BiCMOS LSI using automated macrocell design 使用自动化宏单元设计的500k晶体管定制BiCMOS LSI
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48204
H. Yoshimura, S. Horiguchi, K. Takeya, K. Ishikawa, S. Date, S. Muramoto, H. Yoshino
{"title":"500 k transistor custom BiCMOS LSI using automated macrocell design","authors":"H. Yoshimura, S. Horiguchi, K. Takeya, K. Ishikawa, S. Date, S. Muramoto, H. Yoshino","doi":"10.1109/ISSCC.1989.48204","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48204","url":null,"abstract":"A high-density and quick-turnaround macrocell design method for custom VLSIs is applied to a 500 k-transistor protocol control chip, resulting in a density of about 4000 transistors/mm/sup 2/ using 0.8- mu m BiCMOS technology. An automated adaptive macrocell and a short-time custom VLSI design methodology were developed to make the logic and physical design more adaptable by offering greater variety of bit width, word length, circuit type, and signal terminals. The adaptive macrocell generation procedure consists of a logical description and a physical description with minimum information on the composition of complete macrocells, suitable for all specific uses. The variables providing adaptability are parameterized in this procedure, which is hierarchically described by network information among leaf cells or submacrocells, together with their topological placement information, permitting the adaptive macrocell to be generated automatically. An example of an ALU (arithmetic logic unit) circuit generated as a data-path submacrocell is shown. To verify the effectiveness of the proposed method, various kinds of macrocells were generated and fabricated using the 0.8- mu m, double-metal BiCMOS technology. A packet communication control circuit supporting X.25-based layer 2 and 3 protocols, which was designed by this method, is presented.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132581987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 9 ns, low standby power CMOS PLD with a single-poly EPROM cell 一个9ns，低待机功率CMOS PLD与一个单多EPROM电池
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48268
S. O. Frake, M. Knecht, P. Cacharelis, M. Hart, M. Manley, R. Zeman, R. Ramus
{"title":"A 9 ns, low standby power CMOS PLD with a single-poly EPROM cell","authors":"S. O. Frake, M. Knecht, P. Cacharelis, M. Hart, M. Manley, R. Zeman, R. Ramus","doi":"10.1109/ISSCC.1989.48268","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48268","url":null,"abstract":"The authors describe a 9-ns CMOS programmable logic device (PLD) with a standby current of 10 mu A. The circuit is a 24-pin PLD with 10 I/Os (input/outputs) and 12 dedicated inputs. Each I/O has eight summed-product terms and an output-enable control product term feeding into a programmable macrocell. Most standard 24-pin PLDs can be emulated by selectively programming the macrocell architecture bits. Bit-line precharging circuitry is used to reduce the speed degradation caused by designing for low standby current. 'Ground bounce' is alleviated by controlling the output buffer speed. The circuit has been fabricated in a 1- mu m single-polysilicon CMOS EPROM (electrically programmable read-only memory) technology that has been optimized for speed rather than for packing density. Device and technology characteristics are summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133155298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1-GOPS CMOS programmable video signal processor 1-GOPS CMOS可编程视频信号处理器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48243
T. Yamazaki, S. Komuro, I. Kumata, J. Koshiba
{"title":"A 1-GOPS CMOS programmable video signal processor","authors":"T. Yamazaki, S. Komuro, I. Kumata, J. Koshiba","doi":"10.1109/ISSCC.1989.48243","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48243","url":null,"abstract":"The specifications for a 1-GOPS CMOS programmable video signal processor are presented. To perform the specified functions using a single chip, four macro blocks, each including a fourth-order inner-product circuit, a shift register with switches, a barrel shifter, and a nonlinear mapper (limiter) are used. The adders are provided at the multiplier input for a symmetric FIR (finite impulse response) filter. The macro blocks have the same configuration, and their function can be programmed externally. The blocks are connected to form a systolic array. A carry-ripple adder, which is usually the critical path of both a multiplier and an adder, is not used in this circuit. The layout of the LSI was generated by an automatic layout program. The sixteen multiplier-adders integrated in the chip are sufficient for most standard applications. It is expected that the LSI will be used for digital video equipment for conventional TV, high-definition television systems, and computer vision equipment.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115520180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 10-bit video BiCMOS track-and-hold 一个10位的视频BiCMOS跟踪和保持
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48182
M. Nayebi, B. Wooley
{"title":"A 10-bit video BiCMOS track-and-hold","authors":"M. Nayebi, B. Wooley","doi":"10.1109/ISSCC.1989.48182","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48182","url":null,"abstract":"The authors describe a monolithic track-and-hold circuit with performance competitive with state-of-the art hybrid systems and surpassing that of previously reported monolithic implementations by nearly two orders of magnitude. The circuit has been integrated in an advanced BiCMOS technology. It operates from +or-5 V power supplies and is capable of driving a 50- Omega load with a voltage swing of +or-1 V. The circuit settles to an accuracy of 10 bits in less than 15 ns. The power consumption is 630 mW for a single-ended implementation and 1.2 W for a fully differential configuration. A block diagram of the differential system consisting of two identical track-and-hold circuits with a common switch driver is presented. The performance of the track-and-hold system is summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116481090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A multistep ADC family with efficient architecture 具有高效架构的多步ADC系列
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48214
S. Chin, M. Mayes, R. Filippi
{"title":"A multistep ADC family with efficient architecture","authors":"S. Chin, M. Mayes, R. Filippi","doi":"10.1109/ISSCC.1989.48214","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48214","url":null,"abstract":"A family of 8- and 10-bit A/D (analog/digital) converters has been developed using an efficient multistep architecture. The 10-bit A/D converter requires two 4-bit (two 3-bit for the 8-bit converter) flash cycles and a 3-bit voltage estimator. For the 10-bit converter, the architecture allows a reduction of comparator count to 16 and the resistor count to 96. While the conversion speed is similar to that of conventional half-flash A/D converters, power consumption and die size are lower due to the reduced number of components. The detailed operation of the A/D converter is illustrated, and a summary of test results is given.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122663804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A wideband class-B video output driver 一个宽带b类视频输出驱动程序
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48183
R.A. Blauschild, R. Meyer, D. Linebarger, J. Scotten, L. Burgyan
{"title":"A wideband class-B video output driver","authors":"R.A. Blauschild, R. Meyer, D. Linebarger, J. Scotten, L. Burgyan","doi":"10.1109/ISSCC.1989.48183","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48183","url":null,"abstract":"The authors describe a high-resolution class-B video output driver IC for analog or digital video display systems. The IC, which uses a single 5-V supply, is combined with high-voltage discrete output power transistors to drive either a color or a monochrome CRT (cathode ray tube). The system yields greater bandwidth while consuming one third the power required by conventional class-A CRT drivers. The circuit was fabricated in a 2- mu m oxide-isolated bipolar process with peak f/sub T/ approximately=8 GHz. Using discrete output transistors (f/sub T/=1 GHz, C/sub CB/=2pF), board testing on a CRT with a nominal 10-pF load yielded approximately 15-ns output rise and fall times with 45-V swing and 60-mA slew current limit.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127175096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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