1.4 m晶体管CMOS门阵列与4 ns RAM

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48249

T. Takahashi, M. Kawashima, M. Fujita, I. Kobayashi, K. Arai, T. Okabe

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引用次数: 8

摘要

提出了一种采用0.8 μ m三金属层工艺实现的亚微米CMOS门阵列。该芯片包括1.4 M晶体管，可用作130k逻辑门和38kb SRAM(静态随机存取存储器)，并被封装在一个400引脚的引脚网格阵列封装中。典型的栅极延迟时间为0.35 ns, SRAM访问时间为4.0 ns。给出了工艺参数，并列出了芯片的基本特性。为了证明这种门阵列的可行性，我们制作了一个通用的64-b CPU存储器控制器。时钟驱动器的系统布局和等负载电容使芯片内的最大时钟偏差时间+或1.0 ns。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 1.4 M-transistor CMOS gate array with 4 ns RAM

A submicron CMOS gate array implemented with 0.8- mu m triple-metal-layer process technology is presented. The chip includes 1.4 M transistors which can be used as 130k logic gates, and a 38-kb SRAM (static random-access memory) and is housed in a 400-pin pin-grid array-package. Typical gate delay time is 0.35 ns, and SRAM access time is 4.0 ns. The process parameters are shown, and the basic features of the chip are listed. A memory controller for a general-purpose, 64-b CPU has been fabricated on this gate array in order to prove feasibility. Systematic placement and the equal load capacitance of the clock drivers make maximum clock skew time +or-1.0 ns within the chip.<>

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来源期刊

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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