A 1.4 M-transistor CMOS gate array with 4 ns RAM

Abstract

A submicron CMOS gate array implemented with 0.8- mu m triple-metal-layer process technology is presented. The chip includes 1.4 M transistors which can be used as 130k logic gates, and a 38-kb SRAM (static random-access memory) and is housed in a 400-pin pin-grid array-package. Typical gate delay time is 0.35 ns, and SRAM access time is 4.0 ns. The process parameters are shown, and the basic features of the chip are listed. A memory controller for a general-purpose, 64-b CPU has been fabricated on this gate array in order to prove feasibility. Systematic placement and the equal load capacitance of the clock drivers make maximum clock skew time +or-1.0 ns within the chip.<>