A 1-GOPS CMOS programmable video signal processor

The specifications for a 1-GOPS CMOS programmable video signal processor are presented. To perform the specified functions using a single chip, four macro blocks, each including a fourth-order inner-product circuit, a shift register with switches, a barrel shifter, and a nonlinear mapper (limiter) are used. The adders are provided at the multiplier input for a symmetric FIR (finite impulse response) filter. The macro blocks have the same configuration, and their function can be programmed externally. The blocks are connected to form a systolic array. A carry-ripple adder, which is usually the critical path of both a multiplier and an adder, is not used in this circuit. The layout of the LSI was generated by an automatic layout program. The sixteen multiplier-adders integrated in the chip are sufficient for most standard applications. It is expected that the LSI will be used for digital video equipment for conventional TV, high-definition television systems, and computer vision equipment.<>