A multistep ADC family with efficient architecture

Abstract

A family of 8- and 10-bit A/D (analog/digital) converters has been developed using an efficient multistep architecture. The 10-bit A/D converter requires two 4-bit (two 3-bit for the 8-bit converter) flash cycles and a 3-bit voltage estimator. For the 10-bit converter, the architecture allows a reduction of comparator count to 16 and the resistor count to 96. While the conversion speed is similar to that of conventional half-flash A/D converters, power consumption and die size are lower due to the reduced number of components. The detailed operation of the A/D converter is illustrated, and a summary of test results is given.<>