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IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers最新文献

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A single-chip 2B1Q U-interface transceiver 单片2B1Q u接口收发器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48285
R. Colbeck, R. Gervais, G. Hunt, A. Ahdab, C. Kurowski
{"title":"A single-chip 2B1Q U-interface transceiver","authors":"R. Colbeck, R. Gervais, G. Hunt, A. Ahdab, C. Kurowski","doi":"10.1109/ISSCC.1989.48285","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48285","url":null,"abstract":"A single-chip transceiver designed to meet the ANSI requirements for the U-interface in the integrated services digital network (ISDN) is described. The device utilizes echo cancellation and the 2B1Q line code to achieve high performance in the presence of near-end crosstalk (NEXT) and other impairments. The 2- mu m, single-metal, double-polysilicon, 5-V CMOS VLSI chip includes all necessary analog and digital signal processing blocks so that a network termination or line termination U-interface can be realized with the addition of a passive line termination circuit and a transformer. Operation over 4.7 km of 0.4-mm or 7.5 km of 0.5 mm cable with a bit error rate of 10/sup -7/ is possible. The performance of the second-order delta-sigma analog/digital converter in response to a 10-kHz sinusoid, assuming a noise bandwidth of 40 kHz (-3 dB), is demonstrated.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121821536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A symbolic simulator for analog circuits 用于模拟电路的符号模拟器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48261
W. Sansen, G. Glelen, H. Walscharts
{"title":"A symbolic simulator for analog circuits","authors":"W. Sansen, G. Glelen, H. Walscharts","doi":"10.1109/ISSCC.1989.48261","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48261","url":null,"abstract":"A symbolic simulator, called ISSAC (interactive symbolic analysis of analog circuits), is described. It derives all AC characteristics for analog integrated circuits, both continuous-time and switched-capacitor, CMOS and bipolar. The program provides the designer with insight into the circuit behavior by allowing symbolic calculation of transfer functions, common-mode rejection ratio, power-supply rejection ratio, impedances, and noise. The program is based on a symbolic Equation solution that exploits sparse matrix techniques, followed by an heuristic approximation. It is written in Common LISP. The input is a file in SPICE or SWAP format. The output is a rational form in the symbolic circuit parameters and the complex frequency variables s or z. All filter elements are treated as symbolic parameters; the op amps are considered to be ideal. The symbolic filter function is obtained in 0.156 CPU seconds on a 15 MIPS (million instructions per second) LISP machine. ISAAC has been used extensively for the analysis of op amps, active filters, and switched-capacitor circuits.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122060129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 200 MIPS single-chip 1 k FFT processor 200 MIPS单片1k FFT处理器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48244
J. O'Brien, J. Mather, B. Holland
{"title":"A 200 MIPS single-chip 1 k FFT processor","authors":"J. O'Brien, J. Mather, B. Holland","doi":"10.1109/ISSCC.1989.48244","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48244","url":null,"abstract":"A device is described which is capable of converting real or complex data from the time domain into the frequency domain, or vice versa. Its integrated dual-port workspace RAM, coefficient ROM, and multiple-resource data path allow the computation of a 1024-point complex transform in less than 100 mu s. No external memory is needed. Multiple devices can be connected in parallel to further increase processing benchmarks. The device can also be used as the core processor in the construction of large (>1 k) one- or two-dimensional transforms, but with additional external memory. Provision is also made for the computation of real-only data transforms with commensurate reductions in calculation time. Six devices in parallel will allow a 1 k transform to be computed at 40-MHz sample rate, equivalent to a 200-MHz radix-2 butterfly rate and an 800-MHz multiplication rate. The processor fabricated in 1.4- mu m CMOS technology, is designed for shrinking to a 1 mu m process. The die size is 13.16 mm*13.66 mm, and the device is assembled in an 84-pin PGA package. Power dissipation is 3 W with a 40-MHz system clock.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126597636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Low-temperature operation of silicon bipolar ECL circuits 硅双极ECL电路的低温运行
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48266
J. Cressler, D. Tang, K. Jenkins, G. P. Li
{"title":"Low-temperature operation of silicon bipolar ECL circuits","authors":"J. Cressler, D. Tang, K. Jenkins, G. P. Li","doi":"10.1109/ISSCC.1989.48266","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48266","url":null,"abstract":"Silicon bipolar transistors with current gain as high as 80 at 77 K are described. ECL (emitter-coupled-logic) circuits using these transistors are operational at low temperatures with no degradation in circuit speed observed until about 165 K as compared to its speed at a typical system operating temperature of 358 K (85 degrees C). The key design and performance issues for low-temperature operation of bipolar (or BiCMOS) circuits are addressed. The device used in the investigation is a scaled double-poly self-aligned transistor. Transistor small-signal response measured by standard S-parameter techniques as a function of temperature is shown. The static noise margin improves at low temperatures, suggesting that reduction of circuit logic swings will be possible. State gain can be greater than unity with V/sub L/ less than 200 mV at 85 K provided the pull-up resistance to emitter resistance ratio is kept sufficiently large.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123012786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 12.5 MHz CMOS continuous time bandpass filter 一个12.5 MHz CMOS连续时间带通滤波器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48258
Y.-T. Wang, F. Lu, A. Abidi
{"title":"A 12.5 MHz CMOS continuous time bandpass filter","authors":"Y.-T. Wang, F. Lu, A. Abidi","doi":"10.1109/ISSCC.1989.48258","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48258","url":null,"abstract":"The authors describe a continuous-time bandpass filter integrated in a 3- mu m CMOS technology, with an f/sub 0/ of 12.5 MHz and a 2% fractional bandwidth. The four-pole filter is modeled on two L-C resonators coupled by mutual inductance, resistively terminated at the input and output for maximum power transfer. Each resonator is simulated on the IC by two tunable integrators in negative feedback and is terminated by MOS resistors to define the filter bandwidth. Regulation of f/sub 0/ is obtained by locking an oscillating, consisting of a third identical integrator pair without termination resistors, to an externally supplied reference frequency. The circuits were fabricated on a double-metal, single-polysilicon, 3- mu m CMOS IC. Operation of the chip at a 12.5-MHz center frequency was verified, showing the desired 2% fractional bandwidth.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130924065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
A 3 Gb/s bipolar phase shifter and AGC amplifier 一个3gb /s双极移相器和AGC放大器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48234
H. Rein, R. Reimann, L. Schmidt
{"title":"A 3 Gb/s bipolar phase shifter and AGC amplifier","authors":"H. Rein, R. Reimann, L. Schmidt","doi":"10.1109/ISSCC.1989.48234","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48234","url":null,"abstract":"Two multipurpose bipolar ICs for Gb/s systems fabricated in a 2- mu m standard silicon bipolar technology are presented. The first is a wideband clock phase shifter with continuously adjustable phase (0 to -2 pi ), operating from 300 MHz to 3 GHz, and the second is a single-chip AGC (automatic gain control) amplifier with large dynamic range (40 dB), high voltage gain (40 dB), and high cutoff frequency (2.5 GHz), operating up to 3 Gb/s. The insertion voltage gain versus frequency at the nominal output voltage swing of 400 mV is shown. Flat gain response and nearly constant 3-dB cutoff frequency of 2.55+or-0.05 GHz within the total dynamic range were achieved. The amplifier was driven by a pseudorandom pulse generator at bit rates up to 3 Gb/s. Output eye patterns with nominal voltage swing and wide opening were observed over the dynamic range, and the bit error rate was below the sensitivity of the measuring equipment, 5*10/sup -11/ up to 2.7 Gb/s and increasing to 3*10/sup -10/ at 2.9 Gb/s. Chip micrographs of both circuits are shown.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132111047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An ANSI standard ISDN transceiver chip set 一个ANSI标准的ISDN收发器芯片组
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48279
H. Khorramabadi, O. Agazzi, T. Koh, S. S. Haider, J. Anidjar, D. Cassiday, S. Daubert, C. Gerveshi, S.P. Kumar, M. Lalumia, S. Ollo, T. Peterson, D. Price, P.H. Tracy, R. W. Walden, G. Wilson, M. R. Dwarakanath, J. Kumar, R. F. Shaw, R. Wilson, N. Gottfried, M.L. Heiskanen, W. R. McDonald, N. Ramesh, R. Blake
{"title":"An ANSI standard ISDN transceiver chip set","authors":"H. Khorramabadi, O. Agazzi, T. Koh, S. S. Haider, J. Anidjar, D. Cassiday, S. Daubert, C. Gerveshi, S.P. Kumar, M. Lalumia, S. Ollo, T. Peterson, D. Price, P.H. Tracy, R. W. Walden, G. Wilson, M. R. Dwarakanath, J. Kumar, R. F. Shaw, R. Wilson, N. Gottfried, M.L. Heiskanen, W. R. McDonald, N. Ramesh, R. Blake","doi":"10.1109/ISSCC.1989.48279","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48279","url":null,"abstract":"The authors describe a two-chip ISDN U-interface transceiver based on the American National Standards Institute (ANSI) 2B1Q line code. The two chips are the analog front-end (AFE) which performs the line interfacing and data conversion functions and the digital subscriber loop (DSL) processor which performs the algorithm-specific signal processing (ASSP) functions in the receive path and in addition, the control, maintenance, and access functions (CMA). The ASSP functions are decimation of the sigma-delta modulator output from the AFE, linear and nonlinear echo cancellation, automatic gain control, interpolation, decision feedback equalization, and timing recovery. The CMA provides access to the digital interface and performs functions such as wire polarity check, rate conversion, framing, cyclic redundancy code generation and check, scrambling and descrambling, activation-deactivation, and start-up control. Successful operation of prototype chip sets has been demonstrated in a laboratory environment for a 26-gauge cable of lengths up to 18000 ft.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133722476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array 一个36 kb/2 ns RAM与1 kG/100 ps逻辑门阵列
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48218
S. Isomura, A. Uchida, M. Iwabuchi, K. Ogiue, K. Matsumura, T. Nakamura, K. Yamaguchi
{"title":"A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array","authors":"S. Isomura, A. Uchida, M. Iwabuchi, K. Ogiue, K. Matsumura, T. Nakamura, K. Yamaguchi","doi":"10.1109/ISSCC.1989.48218","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48218","url":null,"abstract":"An LSI device incorporating a 36-kb RAM and a 1k-gate logic array and using a 0.8- mu m sidewall base contact structure (SICOS) transistor process and four-layer metallization, is described. RAM and peripheral logic have been included in one chip to reduce input/output delay and interconnection delay between the RAM and logic. The chip layout is shown together with the circuit schematic of the RAM macro. RAM address access waveforms are shown along with the waveform of a 21-stage ring oscillator. Major device characteristics are summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121968740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 40 MFLOPS 32-bit floating-point processor 一个40 MFLOPS 32位浮点处理器
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48227
S. Komori, H. Takata, T. Tamura, F. Asai, T. Ohno, O. Tomisawa, T. Yamasaki, K. Shima, H. Nishikawa, H. Terada
{"title":"A 40 MFLOPS 32-bit floating-point processor","authors":"S. Komori, H. Takata, T. Tamura, F. Asai, T. Ohno, O. Tomisawa, T. Yamasaki, K. Shima, H. Nishikawa, H. Terada","doi":"10.1109/ISSCC.1989.48227","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48227","url":null,"abstract":"A 40 MFLOPS (million floating-point operations per second), 32-bit floating-point processor (FP) for a single-board data-driven processor is developed using a pipeline configuration called the elastic pipeline structure. Because there is no need to add controls for pipeline flushing by virtue of the data-driven processing principle, it is possible to employ extensively subdivided pipeline stages. The elastic mode of data transfer between pipeline stages and distributed execution controls along the pipeline result in minimum deterioration of the inherent logic switching speed. The structure of the FP is shown together with details of the ALU (arithmetic logic unit) block. The fabrication process and chip specifications are summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126615197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An 8 b 40 MHz CMOS subranging ADC with pipelined wideband S/H 一个8 b 40 MHz的CMOS分位ADC，具有流水线式宽带S/H
IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI: 10.1109/ISSCC.1989.48212
M. Ishikawa, T. Tsukahara
{"title":"An 8 b 40 MHz CMOS subranging ADC with pipelined wideband S/H","authors":"M. Ishikawa, T. Tsukahara","doi":"10.1109/ISSCC.1989.48212","DOIUrl":"https://doi.org/10.1109/ISSCC.1989.48212","url":null,"abstract":"The authors describe an 8-b CMOS subranging ADC (analog/digital converter) with a 40-MHz conversion rate and a 30-MHz effective resolution bandwidth. The subranging architecture makes it possible to produce small ADCs for digital video applications. A combined DAC (digital/analog converter)/subtractor architecture is used to improve the conversion rate and linearity, a bandwidth enhancement technique is employed for a high-precision integrator-type S/H (sample and hold), and a pipelined S/H and comparator architecture is used to improve the conversion rate. A block diagram of the subranging ADC is shown. A micrograph of an ADC chip fabricated using 1- mu m CMOS technology is presented. The chip achieves effective bits of 7.9, 7.3, and 6.5 at 10-MHz, 30-MHz, and 40-MHz sampling rates, respectively, and full-scale input voltages.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115392755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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