{"title":"A 12.5 MHz CMOS continuous time bandpass filter","authors":"Y.-T. Wang, F. Lu, A. Abidi","doi":"10.1109/ISSCC.1989.48258","DOIUrl":null,"url":null,"abstract":"The authors describe a continuous-time bandpass filter integrated in a 3- mu m CMOS technology, with an f/sub 0/ of 12.5 MHz and a 2% fractional bandwidth. The four-pole filter is modeled on two L-C resonators coupled by mutual inductance, resistively terminated at the input and output for maximum power transfer. Each resonator is simulated on the IC by two tunable integrators in negative feedback and is terminated by MOS resistors to define the filter bandwidth. Regulation of f/sub 0/ is obtained by locking an oscillating, consisting of a third identical integrator pair without termination resistors, to an externally supplied reference frequency. The circuits were fabricated on a double-metal, single-polysilicon, 3- mu m CMOS IC. Operation of the chip at a 12.5-MHz center frequency was verified, showing the desired 2% fractional bandwidth.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"45","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48258","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 45
Abstract
The authors describe a continuous-time bandpass filter integrated in a 3- mu m CMOS technology, with an f/sub 0/ of 12.5 MHz and a 2% fractional bandwidth. The four-pole filter is modeled on two L-C resonators coupled by mutual inductance, resistively terminated at the input and output for maximum power transfer. Each resonator is simulated on the IC by two tunable integrators in negative feedback and is terminated by MOS resistors to define the filter bandwidth. Regulation of f/sub 0/ is obtained by locking an oscillating, consisting of a third identical integrator pair without termination resistors, to an externally supplied reference frequency. The circuits were fabricated on a double-metal, single-polysilicon, 3- mu m CMOS IC. Operation of the chip at a 12.5-MHz center frequency was verified, showing the desired 2% fractional bandwidth.<>