一个36 kb/2 ns RAM与1 kG/100 ps逻辑门阵列

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48218

S. Isomura, A. Uchida, M. Iwabuchi, K. Ogiue, K. Matsumura, T. Nakamura, K. Yamaguchi

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引用次数: 9

摘要

本文描述了一种集成了36kb RAM和1k栅极逻辑阵列、采用0.8 μ m侧壁基接触结构(SICOS)晶体管工艺和四层金属化的LSI器件。RAM和外设逻辑集成在一个芯片中，以减少RAM和逻辑之间的输入/输出延迟和互连延迟。芯片布局与RAM宏的电路原理图一起显示。RAM地址访问波形与21级环形振荡器的波形一起显示。总结了主要器件的特点。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array

An LSI device incorporating a 36-kb RAM and a 1k-gate logic array and using a 0.8- mu m sidewall base contact structure (SICOS) transistor process and four-layer metallization, is described. RAM and peripheral logic have been included in one chip to reduce input/output delay and interconnection delay between the RAM and logic. The chip layout is shown together with the circuit schematic of the RAM macro. RAM address access waveforms are shown along with the waveform of a 21-stage ring oscillator. Major device characteristics are summarized.<>

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来源期刊

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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