R. Colbeck, R. Gervais, G. Hunt, A. Ahdab, C. Kurowski
{"title":"A single-chip 2B1Q U-interface transceiver","authors":"R. Colbeck, R. Gervais, G. Hunt, A. Ahdab, C. Kurowski","doi":"10.1109/ISSCC.1989.48285","DOIUrl":null,"url":null,"abstract":"A single-chip transceiver designed to meet the ANSI requirements for the U-interface in the integrated services digital network (ISDN) is described. The device utilizes echo cancellation and the 2B1Q line code to achieve high performance in the presence of near-end crosstalk (NEXT) and other impairments. The 2- mu m, single-metal, double-polysilicon, 5-V CMOS VLSI chip includes all necessary analog and digital signal processing blocks so that a network termination or line termination U-interface can be realized with the addition of a passive line termination circuit and a transformer. Operation over 4.7 km of 0.4-mm or 7.5 km of 0.5 mm cable with a bit error rate of 10/sup -7/ is possible. The performance of the second-order delta-sigma analog/digital converter in response to a 10-kHz sinusoid, assuming a noise bandwidth of 40 kHz (-3 dB), is demonstrated.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48285","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
A single-chip transceiver designed to meet the ANSI requirements for the U-interface in the integrated services digital network (ISDN) is described. The device utilizes echo cancellation and the 2B1Q line code to achieve high performance in the presence of near-end crosstalk (NEXT) and other impairments. The 2- mu m, single-metal, double-polysilicon, 5-V CMOS VLSI chip includes all necessary analog and digital signal processing blocks so that a network termination or line termination U-interface can be realized with the addition of a passive line termination circuit and a transformer. Operation over 4.7 km of 0.4-mm or 7.5 km of 0.5 mm cable with a bit error rate of 10/sup -7/ is possible. The performance of the second-order delta-sigma analog/digital converter in response to a 10-kHz sinusoid, assuming a noise bandwidth of 40 kHz (-3 dB), is demonstrated.<>