{"title":"一个12.5 MHz CMOS连续时间带通滤波器","authors":"Y.-T. Wang, F. Lu, A. Abidi","doi":"10.1109/ISSCC.1989.48258","DOIUrl":null,"url":null,"abstract":"The authors describe a continuous-time bandpass filter integrated in a 3- mu m CMOS technology, with an f/sub 0/ of 12.5 MHz and a 2% fractional bandwidth. The four-pole filter is modeled on two L-C resonators coupled by mutual inductance, resistively terminated at the input and output for maximum power transfer. Each resonator is simulated on the IC by two tunable integrators in negative feedback and is terminated by MOS resistors to define the filter bandwidth. Regulation of f/sub 0/ is obtained by locking an oscillating, consisting of a third identical integrator pair without termination resistors, to an externally supplied reference frequency. The circuits were fabricated on a double-metal, single-polysilicon, 3- mu m CMOS IC. Operation of the chip at a 12.5-MHz center frequency was verified, showing the desired 2% fractional bandwidth.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"45","resultStr":"{\"title\":\"A 12.5 MHz CMOS continuous time bandpass filter\",\"authors\":\"Y.-T. Wang, F. Lu, A. Abidi\",\"doi\":\"10.1109/ISSCC.1989.48258\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe a continuous-time bandpass filter integrated in a 3- mu m CMOS technology, with an f/sub 0/ of 12.5 MHz and a 2% fractional bandwidth. The four-pole filter is modeled on two L-C resonators coupled by mutual inductance, resistively terminated at the input and output for maximum power transfer. Each resonator is simulated on the IC by two tunable integrators in negative feedback and is terminated by MOS resistors to define the filter bandwidth. Regulation of f/sub 0/ is obtained by locking an oscillating, consisting of a third identical integrator pair without termination resistors, to an externally supplied reference frequency. The circuits were fabricated on a double-metal, single-polysilicon, 3- mu m CMOS IC. Operation of the chip at a 12.5-MHz center frequency was verified, showing the desired 2% fractional bandwidth.<<ETX>>\",\"PeriodicalId\":385838,\"journal\":{\"name\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-02-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"45\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1989.48258\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48258","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 45
摘要
作者描述了一种集成在3 μ m CMOS技术中的连续时间带通滤波器,其f/sub /为12.5 MHz,分数带宽为2%。四极滤波器采用互感耦合的两个L-C谐振器,在输入端和输出端阻性端接,以实现最大功率传输。每个谐振器在IC上由两个可调谐的负反馈积分器模拟,并由MOS电阻端接以定义滤波器带宽。f/sub 0/的调节是通过锁定由第三个相同的积分器对组成的振荡来获得的,没有终端电阻,到外部提供的参考频率。该电路是在双金属、单多晶硅、3 μ m CMOS IC上制造的。该芯片在12.5 mhz中心频率下的运行得到了验证,显示出所需的2%分数带宽。
The authors describe a continuous-time bandpass filter integrated in a 3- mu m CMOS technology, with an f/sub 0/ of 12.5 MHz and a 2% fractional bandwidth. The four-pole filter is modeled on two L-C resonators coupled by mutual inductance, resistively terminated at the input and output for maximum power transfer. Each resonator is simulated on the IC by two tunable integrators in negative feedback and is terminated by MOS resistors to define the filter bandwidth. Regulation of f/sub 0/ is obtained by locking an oscillating, consisting of a third identical integrator pair without termination resistors, to an externally supplied reference frequency. The circuits were fabricated on a double-metal, single-polysilicon, 3- mu m CMOS IC. Operation of the chip at a 12.5-MHz center frequency was verified, showing the desired 2% fractional bandwidth.<>