An 8 b 40 MHz CMOS subranging ADC with pipelined wideband S/H

Abstract

The authors describe an 8-b CMOS subranging ADC (analog/digital converter) with a 40-MHz conversion rate and a 30-MHz effective resolution bandwidth. The subranging architecture makes it possible to produce small ADCs for digital video applications. A combined DAC (digital/analog converter)/subtractor architecture is used to improve the conversion rate and linearity, a bandwidth enhancement technique is employed for a high-precision integrator-type S/H (sample and hold), and a pipelined S/H and comparator architecture is used to improve the conversion rate. A block diagram of the subranging ADC is shown. A micrograph of an ADC chip fabricated using 1- mu m CMOS technology is presented. The chip achieves effective bits of 7.9, 7.3, and 6.5 at 10-MHz, 30-MHz, and 40-MHz sampling rates, respectively, and full-scale input voltages.<>