一个5v - 256kbit CMOS闪存EEPROM

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48207

S. D'Arrigo, G. Imondi, G. Santin, M. Gill, R. Cleavelin, S. Spagliccia, E. Tomassetti, S. Lin, A. Nguyen, P. Shah, G. Savarese, D. McElroy

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引用次数: 17

摘要

作者描述了一种256 kbit的闪存EEPROM(电可擦除和可编程只读存储器)设备，它的编程、擦除和读取操作只需要5 V，其性能和成本与最近报道的双电源闪存EEPROM相当，后者需要12 V的编程和擦除，5 V的读取。该存储单元由一个浮栅晶体管和一个合并通栅晶体管组成。该工艺采用阵列非接触式EEPROM (ACEE)，位线采用隧道氧化模块和20v CMOS模块的埋地源/漏极。当对选定的钻头施加适当的电压时，程序和擦除操作使用通过100-AA氧化物隧道的Fowler-Nordheim电流。对该装置及工艺参数进行了总结

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A 5 V-only 256 kbit CMOS flash EEPROM

The authors describe a 256-kbit flash EEPROM (electrically erasable and programmable read-only memory) device which requires only 5 V for program, erase, and read operations and has performance and cost comparable to that of the recently reported dual-power-supply flash EEPROMs, which require 12 V for programming and erase and 5 V for read. The memory cell consists of a floating-gate transistor and a merged-pass-gate transistor. The process is array-contactless EEPROM (ACEE), with buried source/drain for the bit lines with a tunnel oxide module and a 20-V CMOS module. The program and erase operations employ the Fowler-Nordheim current tunneled through 100-AA oxide when the proper electrical voltages are applied to the selected bit. The device and technology parameters are summarized.<>

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来源期刊

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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