1mb的EEPROM

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48211

R. Cernea, G. Samachisa, C. Su, Hui-Fang Tsai, Y. Kao, C. Wang, Y.S. Chen, A. Renninger, T. Wong, J. Brennan, J. Haines

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引用次数: 9

摘要

采用双多晶硅，单金属，n阱CMOS工艺制造了具有5.6 μ m*4.4 μ m单元的1mb闪存EEPROM(电可擦除和可编程只读存储器)。采用双扩散漏极结构来减少n沟道外围器件的热电子退化。对于每个输出，内存被组织成1024行和128列。擦除和编程操作是由一个定时器内部控制，是稳定的温度和电压供应的变化。地址和数据在程序和擦除操作期间被锁存。内部泵为擦除操作产生高电压。6余行和2余列，以提高产量。与阵列单元类似的闪存EEPROM单元被用作冗余电路中的可编程元件。给出了工艺参数。

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A 1 Mb flash EEPROM

A 1-Mb flash EEPROM (electrically erasable and programmable read-only memory) with a 5.6- mu m*4.4- mu m cell is fabricated with a double-polysilicon, single-metal, n-well CMOS process. A double-diffused drain structure is used to reduce hot-electron degradation of n-channel peripheral devices. The memory is organized into 1024 rows and 128 columns for each output. Erase and programming operations are internally controlled by a timer that is stabilized against temperature and voltage supply variations. Addresses and data are latched during program and erase operations. Internal pumps generate the high voltage for the erase operation. Six redundant rows and two redundant columns are provided to enhance yield. Flash EEPROM cells similar to the array cells are used as the programmable elements in the redundancy circuits. Process parameters are given.<>

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来源期刊

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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