{"title":"一个13位，160千赫，差分模拟数字转换器","authors":"S. Ramet","doi":"10.1109/ISSCC.1989.48216","DOIUrl":null,"url":null,"abstract":"The author describes a 13-bit, 160-kHz differential ADC (analog-to-digital converter), and an 80-kHz version, both including a reference circuit delivering two voltages that are symmetrical with respect to the power supply midpoint. These circuits are implemented in the 1.2- mu m CMOS double-metal process using an extra n+ diffusion to accommodate poly/n+ capacitors. Starting from the k-bit linearity requirement for the capacitor array and considering previous results, the bits were partitioned into P=4 bits for the resistor-string and K=9 bits for the capacitor array. The fast Fourier transform (FFT) result is shown for a 5-kHz sine-wave full-scale input sampled at 160 kHz. The performance of the circuit is summarized.<<ETX>>","PeriodicalId":385838,"journal":{"name":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 13-bit, 160 kHz, differential analog to digital converter\",\"authors\":\"S. Ramet\",\"doi\":\"10.1109/ISSCC.1989.48216\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The author describes a 13-bit, 160-kHz differential ADC (analog-to-digital converter), and an 80-kHz version, both including a reference circuit delivering two voltages that are symmetrical with respect to the power supply midpoint. These circuits are implemented in the 1.2- mu m CMOS double-metal process using an extra n+ diffusion to accommodate poly/n+ capacitors. Starting from the k-bit linearity requirement for the capacitor array and considering previous results, the bits were partitioned into P=4 bits for the resistor-string and K=9 bits for the capacitor array. The fast Fourier transform (FFT) result is shown for a 5-kHz sine-wave full-scale input sampled at 160 kHz. The performance of the circuit is summarized.<<ETX>>\",\"PeriodicalId\":385838,\"journal\":{\"name\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-02-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1989.48216\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1989.48216","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
摘要
作者描述了一个13位，160 khz差分ADC(模数转换器)和一个80 khz版本，两者都包括一个参考电路，提供相对于电源中点对称的两个电压。这些电路在1.2 μ m CMOS双金属工艺中实现，使用额外的n+扩散来容纳多/n+电容器。从电容阵列的K位线性要求出发，并考虑到之前的结果，将位划分为电阻串的P=4位和电容阵列的K=9位。快速傅里叶变换(FFT)结果显示了采样频率为160 kHz的5 kHz正弦波全尺寸输入。对该电路的性能进行了总结
A 13-bit, 160 kHz, differential analog to digital converter
The author describes a 13-bit, 160-kHz differential ADC (analog-to-digital converter), and an 80-kHz version, both including a reference circuit delivering two voltages that are symmetrical with respect to the power supply midpoint. These circuits are implemented in the 1.2- mu m CMOS double-metal process using an extra n+ diffusion to accommodate poly/n+ capacitors. Starting from the k-bit linearity requirement for the capacitor array and considering previous results, the bits were partitioned into P=4 bits for the resistor-string and K=9 bits for the capacitor array. The fast Fourier transform (FFT) result is shown for a 5-kHz sine-wave full-scale input sampled at 160 kHz. The performance of the circuit is summarized.<>
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