一个8 ns BiCMOS 1 Mb ECL SRAM，具有可配置的存储器阵列大小

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers Pub Date : 1989-02-15 DOI:10.1109/ISSCC.1989.48223

H. Tran, K. Fung, D. Bell, R. Chapman, M. Harward, T. Suzuki, R. Havemann, R. Eklund, R. Fleck, D. Le, C. Wei, N. Iyengar, M. Rodder, R. Haken, D. Scott

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引用次数: 22

摘要

采用0.8 μ m的BiCMOS工艺制备了1 mb *1 BiCMOS ECL(发射器耦合逻辑)I/O SRAM(静态随机存取存储器)。该存储器件采用76 μ m/sup /全cmos六晶体管存储单元、双mos电流源BiCMOS位线传感方案、BiCMOS电流源电压参考网络和低电容负载块线译码电路实现8ns的访问时间。可配置的内存阵列大小架构允许内存大小从64 kb到1 Mb，增量为64 kb，外围电路不改变。显示了六晶体管单元布局，并说明了存储块结构。电源电流对工作频率的低依赖性显示了ECL电路在设计中的影响。总结了SRAM的特点

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An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size

A 1-Mb*1 BiCMOS ECL (emitter-coupled-logic) I/O SRAM (static random access memory) is fabricated using a 0.8- mu m BiCMOS process. This memory device utilizes a 76- mu m/sup 2/ full-CMOS six-transistor memory cell, a dual-MOS current-source BiCMOS bit line sensing scheme, a BiCMOS current-source voltage reference network, and a low-capacitance load block line decoding circuit to achieve 8-ns access time. The configurable memory array size architecture allows for memory sizes from 64 kb up to 1 Mb in 64 kb increments with no change in the peripheral circuits. The six-transistor cell layout is shown, and the memory block architecture is illustrated. The low dependence of power supply current on the operating frequency shows the impact of ECL circuits in the design. Characteristics of the SRAM are summarized.<>

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来源期刊

IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers

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