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Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting最新文献

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0.5 /spl mu/m silicon bipolar transistor technology for analog applications 0.5 /spl mu/m硅双极晶体管技术用于模拟应用
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587897
H. Nakajima, N. Itoh, K. Inou, T. Iinuma, S. Matsuda, C. Yoshino, Y. Katsumata, H. Iwai
{"title":"0.5 /spl mu/m silicon bipolar transistor technology for analog applications","authors":"H. Nakajima, N. Itoh, K. Inou, T. Iinuma, S. Matsuda, C. Yoshino, Y. Katsumata, H. Iwai","doi":"10.1109/BIPOL.1994.587897","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587897","url":null,"abstract":"A silicon bipolar technology for low power analog applications with a 0.5 /spl mu/m design rule has been developed. A maximum fT value of 24 GHz (@ VCE=2 V, IC=260 /spl mu/A) is obtained, as well as a 1/32 prescaler free-run frequency of 8.0 GHz (@ VCC=5 V, IC=600 /spl mu/A).","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124298058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High fan-in circuit design 高扇入电路设计
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587847
L. Clark, G. Taylor
{"title":"High fan-in circuit design","authors":"L. Clark, G. Taylor","doi":"10.1109/BIPOL.1994.587847","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587847","url":null,"abstract":"A review of high fan-in circuit design in contemporary logic technologies is presented. This is followed by a description of a BiNMOS circuit structure which allows the construction of large fan-in, dynamic logical NAND or OR functions. Power and reliability considerations such as BJT reverse V/sub be/ and MOS hot electron protection are included. Application of the circuit in the 3.3 V, 100 MHz, implementation of the Pentium Microprocessor on a 0.6 mm BiNMOS process is discussed.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121363081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Design techniques for analog BiCMOS circuits 模拟BiCMOS电路的设计技术
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587865
K. Sone, M. Yotsuyanagi
{"title":"Design techniques for analog BiCMOS circuits","authors":"K. Sone, M. Yotsuyanagi","doi":"10.1109/BIPOL.1994.587865","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587865","url":null,"abstract":"This paper describes design techniques for analog BiCMOS circuits. Comparison on such performance as transconductance, matching, noise, and speed of MOS and bipolar transistors is summarized. BiCMOS op amp circuits as a basic analog circuit are discussed. Other design examples such as a high-speed A/D converter LSI, a PLL frequency synthesizer LSI, and a read/write control LSI for a floppy disk drive are introduced.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115713534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Influence of back-end thermal processing on polysilicon-monosilicon contact resistance due to dopant deactivation 掺杂失活后热处理对多晶硅-单晶硅接触电阻的影响
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587904
A. Perera, W. Taylor, M. Orlowski
{"title":"Influence of back-end thermal processing on polysilicon-monosilicon contact resistance due to dopant deactivation","authors":"A. Perera, W. Taylor, M. Orlowski","doi":"10.1109/BIPOL.1994.587904","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587904","url":null,"abstract":"The effect of post-planarization rapid thermal anneal (RTA) steps on polysilicon-monosilicon contact resistance is critically dependent on the thermal requirements of the specific planarization technique used. While these RTA steps were found to increase R/sub c,poly/n+/ for chemical mechanical polishing (CMP) type low or zero thermal budget back-end processes, they decreased R/sub c,poly/n+/ when furnace glass reflow anneals were used. For a CMP back-end process when a high temperature (/spl ges/1000/spl deg/C) RTA is used to form the shallow n/sup +/ emitter junction, all subsequent anneals need to be carefully optimized to avoid drastic increases in R/sub c,poly/n+/-for a 1065/spl deg/C emitter RTA and 850/spl deg/C RTA process, a 700/spl deg/C RTA caused a 62% increase for a 30 sec anneal and a 125% increase for a 300 sec anneal.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116051205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 1.1 V bootstrapped bipolar CMOS logic (B/sup 2/CMOS) for low power systems 用于低功耗系统的1.1 V自启动双极CMOS逻辑(B/sup 2/CMOS)
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587850
S. Embabi, A. Bellaouar, K. Islam
{"title":"A 1.1 V bootstrapped bipolar CMOS logic (B/sup 2/CMOS) for low power systems","authors":"S. Embabi, A. Bellaouar, K. Islam","doi":"10.1109/BIPOL.1994.587850","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587850","url":null,"abstract":"This paper reports on a BiCMOS logic gate which is capable of operating down to 1.1 V and can, hence, be used for low power systems. The proposed B/sup 2/CMOS uses a non-complementary BiCMOS process. Simulations have shown that the B/sup 2/CMOS gate outperforms CMOS and BiNMOS gates at 3 V and below. The cross-over capacitance/fanout of the B/sup 2/CMOS gate is 100 fF (i.e. fanout of 4) at 1.5 V. The delay-to-load sensitivity of the B/sup 2/CMOS is 220 ps/pF (8 ps/fanout) which is one order of magnitude smaller than that of CMOS at 1.5 V.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129818068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simple technique for improving the hot-carrier reliability of single-poly bipolar transistors 提高单聚双极晶体管热载流子可靠性的简单技术
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587895
S. Kosier, M. DeLaus, A. Wei, peixiong zhao, A. Martinez
{"title":"Simple technique for improving the hot-carrier reliability of single-poly bipolar transistors","authors":"S. Kosier, M. DeLaus, A. Wei, peixiong zhao, A. Martinez","doi":"10.1109/BIPOL.1994.587895","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587895","url":null,"abstract":"It is shown experimentally and through simulation that reduced screen oxide thickness leads to increased breakdown voltage of the emitter-base junction (BV/sub ebo/) and reduced peak electric field at breakdown, which translates into improved hot-carrier reliability. The effect of reduced screen oxide thickness on the peak cutoff frequency is minimal. For these devices, thinning the screen oxide from 55 to 35 nm increases BV/sub ebo/ by 0.2 V, improves the hot-carrier-induced excess base current by more than an order of magnitude at a base-emitter voltage of 0.6 V, and degrades the peak cutoff frequency by only 3 percent.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128148449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SiGe bipolar ICs for 20 Gb/s optical transmitter 用于20gb /s光发射机的SiGe双极ic
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587886
T. Hashimoto, H. Tezuka, F. Sato, M. Soda, T. Suzaki, T. Tatsumi, T. Tashiro
{"title":"SiGe bipolar ICs for 20 Gb/s optical transmitter","authors":"T. Hashimoto, H. Tezuka, F. Sato, M. Soda, T. Suzaki, T. Tatsumi, T. Tashiro","doi":"10.1109/BIPOL.1994.587886","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587886","url":null,"abstract":"SiGe bipolar ICs, a selector, a multiplier and a D-type flip-flop, have been developed for a 20 Gb/s optical transmitter by using a self-aligned SiGe base bipolar transistor with bonded SOI technology. In the selector IC and the multiplier IC, an internal high speed clock buffer circuit accomplishes stable operation under a single clock input condition.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"44 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131573736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A novel sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump 一种新型的带充电泵的低于2.0 V的BiCMOS逻辑电路
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587849
H. Okamura, T. Atsumo, K. Takeda, M. Takada, K. Imai, Y. Kinoshita, T. Yamazaki
{"title":"A novel sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump","authors":"H. Okamura, T. Atsumo, K. Takeda, M. Takada, K. Imai, Y. Kinoshita, T. Yamazaki","doi":"10.1109/BIPOL.1994.587849","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587849","url":null,"abstract":"A novel BiCMOS logic circuit with a BiCMOS charge pump is described. This BiCMOS logic circuit operating with very small input capacitance at low power supply, achieves more than 10 times the speed of CMOS.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"2019 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134284478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Advanced modelling of distortion effects in bipolar transistors using the Mextram model 利用Mextram模型对双极晶体管畸变效应进行高级建模
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587854
L. Vreede, H. C. Graaff, Koenraad Mouthaan, M. Kok, J. Tauritz, R. Baets
{"title":"Advanced modelling of distortion effects in bipolar transistors using the Mextram model","authors":"L. Vreede, H. C. Graaff, Koenraad Mouthaan, M. Kok, J. Tauritz, R. Baets","doi":"10.1109/BIPOL.1994.587854","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587854","url":null,"abstract":"Modelling of distortion effects in bipolar transistors due to the onset of quasi saturation is considered. Computational results obtained using Mextram and Gummel Poon models as implemented in a harmonic balance simulator are compared with measured results.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115884431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A quasi-static approach for modeling the influence of emitter stored charge on the high frequency small signal a.c. response of bipolar transistors 用准静态方法模拟发射极储存电荷对双极晶体管高频小信号交流响应的影响
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587853
J. Hamel
{"title":"A quasi-static approach for modeling the influence of emitter stored charge on the high frequency small signal a.c. response of bipolar transistors","authors":"J. Hamel","doi":"10.1109/BIPOL.1994.587853","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587853","url":null,"abstract":"A quasi-static approach is developed to model the effects of emitter stored charge on the high frequency response of bipolar transistors.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122786133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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