A 1.1 V bootstrapped bipolar CMOS logic (B/sup 2/CMOS) for low power systems

Abstract

This paper reports on a BiCMOS logic gate which is capable of operating down to 1.1 V and can, hence, be used for low power systems. The proposed B/sup 2/CMOS uses a non-complementary BiCMOS process. Simulations have shown that the B/sup 2/CMOS gate outperforms CMOS and BiNMOS gates at 3 V and below. The cross-over capacitance/fanout of the B/sup 2/CMOS gate is 100 fF (i.e. fanout of 4) at 1.5 V. The delay-to-load sensitivity of the B/sup 2/CMOS is 220 ps/pF (8 ps/fanout) which is one order of magnitude smaller than that of CMOS at 1.5 V.