0.5 /spl mu/m硅双极晶体管技术用于模拟应用

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI:10.1109/BIPOL.1994.587897

H. Nakajima, N. Itoh, K. Inou, T. Iinuma, S. Matsuda, C. Yoshino, Y. Katsumata, H. Iwai

{"title":"0.5 /spl mu/m硅双极晶体管技术用于模拟应用","authors":"H. Nakajima, N. Itoh, K. Inou, T. Iinuma, S. Matsuda, C. Yoshino, Y. Katsumata, H. Iwai","doi":"10.1109/BIPOL.1994.587897","DOIUrl":null,"url":null,"abstract":"A silicon bipolar technology for low power analog applications with a 0.5 /spl mu/m design rule has been developed. A maximum fT value of 24 GHz (@ VCE=2 V, IC=260 /spl mu/A) is obtained, as well as a 1/32 prescaler free-run frequency of 8.0 GHz (@ VCC=5 V, IC=600 /spl mu/A).","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"0.5 /spl mu/m silicon bipolar transistor technology for analog applications\",\"authors\":\"H. Nakajima, N. Itoh, K. Inou, T. Iinuma, S. Matsuda, C. Yoshino, Y. Katsumata, H. Iwai\",\"doi\":\"10.1109/BIPOL.1994.587897\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A silicon bipolar technology for low power analog applications with a 0.5 /spl mu/m design rule has been developed. A maximum fT value of 24 GHz (@ VCE=2 V, IC=260 /spl mu/A) is obtained, as well as a 1/32 prescaler free-run frequency of 8.0 GHz (@ VCC=5 V, IC=600 /spl mu/A).\",\"PeriodicalId\":373721,\"journal\":{\"name\":\"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-10-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1994.587897\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1994.587897","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

开发了一种低功耗模拟应用的硅双极技术，设计规则为0.5 /spl mu/m。最大fT值为24 GHz (@ VCE=2 V, IC=260 /spl mu/A)，以及1/32预分频器自由运行频率为8.0 GHz (@ VCC=5 V, IC=600 /spl mu/A)。

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0.5 /spl mu/m silicon bipolar transistor technology for analog applications

A silicon bipolar technology for low power analog applications with a 0.5 /spl mu/m design rule has been developed. A maximum fT value of 24 GHz (@ VCE=2 V, IC=260 /spl mu/A) is obtained, as well as a 1/32 prescaler free-run frequency of 8.0 GHz (@ VCC=5 V, IC=600 /spl mu/A).

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Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting

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