Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting最新文献

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A 6.8 mA closed-loop monolithic buffer with 120 MHz bandwidth, 4000 V//spl mu/S slew rate and /spl plusmn/12 V signal compatibility 一个6.8 mA闭环单片缓冲器,120 MHz带宽,4000 V//spl mu/S转换速率和/spl plusmn/ 12v信号兼容
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587846
D. Bowers
{"title":"A 6.8 mA closed-loop monolithic buffer with 120 MHz bandwidth, 4000 V//spl mu/S slew rate and /spl plusmn/12 V signal compatibility","authors":"D. Bowers","doi":"10.1109/BIPOL.1994.587846","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587846","url":null,"abstract":"A closed-loop current-feedback high-speed monolithic buffer is described which is capable of operation from /spl plusmn/18 V supplies with 6.8 mA of supply current. A 4000 V//spl mu/S slew-rate and 120 MHz bandwidth are achieved together with accuracies approaching those of general purpose op-amps.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121379549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Single crystal silicon contacted double self-aligned bipolar junction transistor by selective epitaxial growth 单晶硅接触双自对准双极结晶体管的选择性外延生长
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587861
Chitra K. Subramanian, G. Neudeck
{"title":"Single crystal silicon contacted double self-aligned bipolar junction transistor by selective epitaxial growth","authors":"Chitra K. Subramanian, G. Neudeck","doi":"10.1109/BIPOL.1994.587861","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587861","url":null,"abstract":"A novel single crystal silicon contacted double self-aligned transistor (DST) structure, that uses vertical seed epitaxial lateral overgrowth (VELO) is demonstrated. When scaled to smaller dimensions, this structure can provide an 18% improvement in ECL circuit speed.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114298579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and realization of low-noise, high-gain Si-bipolar transimpedance preamplifiers for 10 Gb/s optical-fiber links 10gb /s光纤链路低噪声、高增益硅双极透阻前置放大器的设计与实现
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587885
M. Neuhauser, H. Rein, H. Wernz
{"title":"Design and realization of low-noise, high-gain Si-bipolar transimpedance preamplifiers for 10 Gb/s optical-fiber links","authors":"M. Neuhauser, H. Rein, H. Wernz","doi":"10.1109/BIPOL.1994.587885","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587885","url":null,"abstract":"Design principles and circuit configurations of Si-bipolar preamplifiers for 10 Gb/s optical-fiber links are discussed. The ICs were fabricated in an advanced production technology. High transimpedance (710 /spl Omega/) and low equivalent input noise current density (averaged: 9 pA//spl radic/(Hz)) were achieved.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127574268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 1.3-ns 32-word by 32-bit three-port BiCMOS register file 一个1.3-ns 32字× 32位三端口BiCMOS寄存器文件
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587868
Chin-Chieh Chao, B. Wooley
{"title":"A 1.3-ns 32-word by 32-bit three-port BiCMOS register file","authors":"Chin-Chieh Chao, B. Wooley","doi":"10.1109/BIPOL.1994.587868","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587868","url":null,"abstract":"This paper describes a CMOS multiport static memory cell that can be accessed through a low-voltage-swing read path. With this cell it is possible to achieve read access times comparable to those of pure bipolar memories while preserving the high density of CMOS memories. An experimental 32-word by 32-bit three-port register file has been designed and implemented using the cell. This circuit was fabricated in a 0.6-/spl mu/m BiCMOS technology and achieves a pin-to-pin access time of 1.3 ns at 20/spl deg/C.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133289061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A high speed bipolar transistor using 2-step epitaxial base technology 采用两步外延基片技术的高速双极晶体管
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587858
K. Yamano, H. Fujimaki, H. Yokouchi, K. Ohshima, K. Suzuki
{"title":"A high speed bipolar transistor using 2-step epitaxial base technology","authors":"K. Yamano, H. Fujimaki, H. Yokouchi, K. Ohshima, K. Suzuki","doi":"10.1109/BIPOL.1994.587858","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587858","url":null,"abstract":"The 2-step selective epitaxial growth technology has been extended to the base formation of the transistor for the purpose of improving the cut-off frequency (fT), the base-collector junction capacitance (Cjc) and the base resistance (Rb) which are very influential parameters for the high speed performance of bipolar LSI. By utilizing the 2-step base epitaxy, the actual base width reduction that improves the base transit time of the electrons has been able to be realized, although the total base epitaxial thickness that affects Cjc has not been changed. As a result, the maximum cut-off frequency (fTmax) has been improved to 40 GHz in the case that the doping layer thickness has been reduced to 30 nm by 2-step base epitaxy, though fTmax remains 14 GHz in the case that the 150 nm single epitaxial layer has been deposited.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121711801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A speed, power, and supply noise evaluation of ECL driver circuits ECL驱动电路的速度、功率和供电噪声评估
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587876
N. Jouppi, S. Sidiropoulos, S. Menon
{"title":"A speed, power, and supply noise evaluation of ECL driver circuits","authors":"N. Jouppi, S. Sidiropoulos, S. Menon","doi":"10.1109/BIPOL.1994.587876","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587876","url":null,"abstract":"Active pull-down circuits can generate less supply noise while having faster circuit delays and dissipating less power than conventional emitter follower circuits. CML or ECDL resistive pullups are quieter but have poor speed-power performance.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114893226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 2.7 V 800 MHz-2.1 GHz transceiver chipset for mobile radio applications in 25 GHz f/sub t/ Si-bipolar 2.7 V 800mhz -2.1 GHz收发器芯片组,适用于25 GHz f/sub / si双极移动无线电应用
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587888
W. Veit, J. Fenk, S. Ganser, K. Hadjizada, S. Heinen, H. Herrmann, P. Sehrig
{"title":"A 2.7 V 800 MHz-2.1 GHz transceiver chipset for mobile radio applications in 25 GHz f/sub t/ Si-bipolar","authors":"W. Veit, J. Fenk, S. Ganser, K. Hadjizada, S. Heinen, H. Herrmann, P. Sehrig","doi":"10.1109/BIPOL.1994.587888","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587888","url":null,"abstract":"A 800 MHz-2.1 GHz, 2.7 V transceiver chipset for mobile radio which includes transmitter with direct conversion quadrature modulator, IF and RF frequency synthesizing, receiver with LNA, mixer, programmable 80 dB-IF-amplifier and quadrature demodulator Is reported. The /spl sim/4 mm/sup 2/, 25 GHz f/sub t/ bipolar chips consume <250 mW.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124016175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A fully-compensated APD circuit with 10:1 ratio between active and inactive current 全补偿APD电路,有功电流和无功电流比为10:1
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587874
N. Jouppi
{"title":"A fully-compensated APD circuit with 10:1 ratio between active and inactive current","authors":"N. Jouppi","doi":"10.1109/BIPOL.1994.587874","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587874","url":null,"abstract":"An active pull-down (APD) circuit is presented which can provide a 10:1 ratio between active and inactive currents. The new APD circuit is compensated for variations in process, supply, and temperature via a clamp voltage.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115198189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 40 volt silicon complementary bipolar technology for high-precision and high-frequency analog circuits 用于高精度和高频模拟电路的40伏硅互补双极技术
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587900
R. Bashir, J. De Santis, D. Chen, F. Hébert, A. Ramde, P. Maghsoudnia, H. You, P. Meng, F. Moraveji, R. Razouk
{"title":"A 40 volt silicon complementary bipolar technology for high-precision and high-frequency analog circuits","authors":"R. Bashir, J. De Santis, D. Chen, F. Hébert, A. Ramde, P. Maghsoudnia, H. You, P. Meng, F. Moraveji, R. Razouk","doi":"10.1109/BIPOL.1994.587900","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587900","url":null,"abstract":"A high performance and low cost complementary bipolar technology has been developed for the realization of high-precision and high-frequency analog circuits. The technology, referred to as VIP-3 (Vertically Integrated PNP-3), offers transistors with typical BV/sub ceo/ of NPN and PNP transistors at 45 and 60 volts, respectively. In addition, the technology offers BV/sub ceo//spl times/f/sub t//h/sub fe//spl times/Va figures of merit in excess of 135 GHz/spl middot/V/20,000 V for NPN and 130 GHz/spl middot/V/6,500 V for PNP.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134190782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Advanced process technology for a 40-GHz fT self-aligned bipolar LSI 40ghz fT自对准双极LSI的先进工艺技术
Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting Pub Date : 1994-10-10 DOI: 10.1109/BIPOL.1994.587864
T. Hashimoto, S. Satoh, K. Yagi, Y. Tamaki, T. Shiba
{"title":"Advanced process technology for a 40-GHz fT self-aligned bipolar LSI","authors":"T. Hashimoto, S. Satoh, K. Yagi, Y. Tamaki, T. Shiba","doi":"10.1109/BIPOL.1994.587864","DOIUrl":"https://doi.org/10.1109/BIPOL.1994.587864","url":null,"abstract":"This paper describes an optimum rapid thermal processing technology which is suitable for a 40 GHz cut-off frequency (fT) bipolar LSI. Three new techniques have been developed for this purpose. One is in-situ phosphorus doped polysilicon (IDP) emitter technique for reducing thermal budget. Rapid thermal annealing (RTA) technique is used to reduce the emitter-base junction leakage current and to form a shallow junction. And low damage dry etching technique reduces thermal budget for recovery of silicon surface. Using this new technology, high fT of 40 GHz and low E-B junction leakage current have been achieved.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121907828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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