T. Hashimoto, S. Satoh, K. Yagi, Y. Tamaki, T. Shiba
{"title":"Advanced process technology for a 40-GHz fT self-aligned bipolar LSI","authors":"T. Hashimoto, S. Satoh, K. Yagi, Y. Tamaki, T. Shiba","doi":"10.1109/BIPOL.1994.587864","DOIUrl":null,"url":null,"abstract":"This paper describes an optimum rapid thermal processing technology which is suitable for a 40 GHz cut-off frequency (fT) bipolar LSI. Three new techniques have been developed for this purpose. One is in-situ phosphorus doped polysilicon (IDP) emitter technique for reducing thermal budget. Rapid thermal annealing (RTA) technique is used to reduce the emitter-base junction leakage current and to form a shallow junction. And low damage dry etching technique reduces thermal budget for recovery of silicon surface. Using this new technology, high fT of 40 GHz and low E-B junction leakage current have been achieved.","PeriodicalId":373721,"journal":{"name":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1994.587864","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper describes an optimum rapid thermal processing technology which is suitable for a 40 GHz cut-off frequency (fT) bipolar LSI. Three new techniques have been developed for this purpose. One is in-situ phosphorus doped polysilicon (IDP) emitter technique for reducing thermal budget. Rapid thermal annealing (RTA) technique is used to reduce the emitter-base junction leakage current and to form a shallow junction. And low damage dry etching technique reduces thermal budget for recovery of silicon surface. Using this new technology, high fT of 40 GHz and low E-B junction leakage current have been achieved.