Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)最新文献

{"title":"Threshold voltage control for deep sub-micrometer fully depleted SOI MOSFET","authors":"Xiangli Li, S. Parke, B. Wilamowski","doi":"10.1109/UGIM.2003.1225744","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225744","url":null,"abstract":"In this paper, the threshold voltage of fully depleted silicon on insulator device with geometry scale down below 100 nm is investigated deeply. All the device simulations are performed using SILVACO Atlas device simulator. Several ways to control the threshold voltage are proposed and simulated. Threshold voltage changing with the silicon film thickness, channel doping concentration, gate oxide thickness and gate electrode work function is simulated. One short channel NMOS and one PMOS FDSOI device structure with effective channel length 90 nm and 30 nm silicon film thickness are designed.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121427226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A laboratory information management system (LIMS) for an academic microchip fabrication facility","authors":"R. Hendricks, M.R. Learn","doi":"10.1109/UGIM.2003.1225703","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225703","url":null,"abstract":"A relational database laboratory information management system for managing the personnel, facilities, equipment, and instruments associated with a university microelectronics facility is described. Emphasis has been placed on assuring personnel safety. The system includes capabilities for managing training and access to facilities, instruments and tools, for monitoring task assignments to personnel, for tracking inventories of supplies and capital property, and for handling maintenance of both facilities and equipment. There is a built-in mail system that allows communications with personnel based on a wide range of sorting choices including user classification and facility and instrument access rights. As is unique to university facilities, the system is also capable of tracking courses that may be taught in different laboratories. The LIMS gathers data from an unlimited number of computers in an unlimited number of widely separated facilities over a distributed computer network using TCP/IP communications over the University LAN and a Microsoft SQL 2000 Server. We have used coding technologies that allow LIMS administrators to add and delete an unlimited number of users, facilities, instruments, inventory items, and courses. The system is thus expansible and capable of handling the smallest to the largest facilities without any recoding. User access is via several custom programs coded in VB and via protected WWW access on pages generated in HTML and with active server pages (ASP) from a Microsoft IIS server. Both the VB programs and the ASP pages are developed in a highly modular form with security controls that allow the laboratory administrators to control access to each module at three levels-none, read only, and read/write. The code makes use of a large number (currently over 100) SQL 2000 stored procedures. These procedures make it easy to perform complex SQL operations. Data integrity is maintained using a strategy of using multiple servers to separate various server functions (FTP, HTTP, and SQL) and by using multiple levels of backup. The SQL 2000 database is backed up dynamically and daily to a separate PC, and the other servers (FTP and HTTP) are backed up daily over the University LAN using Tivoli.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"PP 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126446824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"System approach for low 1/f noise, high IP2 dynamic range CMOS mixer design","authors":"A. R. Petrov","doi":"10.1109/UGIM.2003.1225700","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225700","url":null,"abstract":"This paper presents system approach considerations for an RF Downconversion mixer design with low 1/f noise, improved second-order intermodulation distortion and low local oscillator (LO) signal reradiation. The intended application is for direct-conversion and ultra low intermediate frequency (IF) receiver systems. The mixer, implemented in a standard 3.3 V 0.35 /spl mu/m CMOS process, achieves a second-order input intercept point (IIP2) of at least +80 dBm. The design utilizes a 25% duty cycle square wave LO control signal with single to differential output sampling mixer architecture to enhance DC offset rejection and improve mixer IIP2 performance. Local oscillator signal waveforms are optimized to minimize undesirable LO signal leakage and LO self-mixing. External and intrinsic noises in the proposed sampling mixer are analyzed using time and frequency domain methods. Analytically calculated and measured results are compared. In addition, direct-conversion receiver system architecture advantages, inherent problems analysis and second-order intermodulation background are given.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121965917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low-voltage low-power 1.5 GHz CMOS LNA design","authors":"Zhang-fa Liu, S. Parke","doi":"10.1109/UGIM.2003.1225760","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225760","url":null,"abstract":"A low-voltage and low-power 1.5 GHz low-noise amplifier in 0.18 /spl mu/m CMOS technology for GPS application is designed, this LNA has 28.7 dB gain with 0.2 dB noise figure from 1.0 V supply voltage. Basic noise analysis and design method are presented in this paper.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125992678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"WIMS comprehensive education program","authors":"L. McAfee","doi":"10.1109/UGIM.2003.1225689","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225689","url":null,"abstract":"The Michigan Wireless Integrated MicroSystems (WIMS) Engineering Research Center (ERC) has a comprehensive education program to serve pre-college (K-12) education, university education, and practicing professionals and society. In this paper, descriptions of the three components and some education programs and results are provided. The highlight of the WIMS Education thrust is the ability to deliver/disseminate/transfer comprehensive quality knowledge-based education opportunities to a diverse pre-college and university students population.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126111855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An overview of algorithms in Gnucap","authors":"A. Davis","doi":"10.1109/UGIM.2003.1225766","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225766","url":null,"abstract":"This paper will present an overview of the algorithms in Gnucap. Gnucap is a mixed-signal circuit simulator. Algorithms to be presented include event driven analog simulation, the use of queues to accelerate simulation of large circuits, implicit mixed-mode simulation, where the simulator automates the interface between analog and digital portions of the circuit. These algorithms provide equivalent accuracy to Spice with significant speedup for some classes of circuits, including large mostly passive circuits with a few active devices, and large mixed-mode circuits with latency. An overview of work in progress will also be given. This includes cached model evaluation, which will exploit hierarchy and duplication in the circuit, and true multi-rate simulation.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124375601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A simulated annealing approach for automatic extraction of device and material parameters of MOS with SiO/sub 2//high-K gate stacks","authors":"Fei Li, S. Mudanai, Yang-yu Fan, Wei Zhao, L. Register, S. Banerjee","doi":"10.1109/UGIM.2003.1225729","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225729","url":null,"abstract":"A program with ability to extract device and material parameters of MOS capacitors with nanometer scale effective oxide thicknesses (EOTs) SiO/sub 2//high-K gate dielectrics from experimental gate capacitance (C-V) and gate leakage current (I-V) with high accuracy in a few minutes is demonstrated. Simulated annealing algorithm was used as the optimisation approach. The device parameters such as EOTs, surface substrate doping, flatband voltage and polysilicon doping (if applicable) can be extracted from C-V data, and potentially band offsets, dielectric constants and tunneling masses can be extracted from I-V data of single or multiplayer gate stacks.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127926231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental investigation of the mechanism for CMP micro-scratch formation","authors":"S. Aytes, J. S. Armstrong, K.A. Mortensen, C. Russell, K. Ross, J. E. Giraud, D. Hooper, H.M. Alexander, T. Corsetti, M. Nelson, M. Engle, J. Prasad","doi":"10.1109/UGIM.2003.1225707","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225707","url":null,"abstract":"CMP (chemical mechanical planarization) micro-scratches are yield and reliability limiting defects in semiconductor production. Electrical shorts, between vias or metal lines, are the most likely failure modes. As device geometries decrease, the probability of a micro-scratch causing a device failure increases. Therefore, understanding of the mechanisms involved in micro-scratch formation becomes increasingly important for good yield and reliability. A mechanism for the formation of micro-scratches and the experimental results in support of the mechanism are presented. It is proposed that micro-scratches are caused primarily by slurry particles that pack into the polish pad fibers during polish (glazing). Once packed into the pad, the silica particles agglomerate. This is especially true if the silica particles are exposed to pH less than ten at the end of the polish or in between polishes. During ex-situ pad conditioning, the agglomerated silica is fractured and loosened from the pad fibers but not removed from the pad surface. The fractured pieces of silica cause micro-scratches, as they break apart during the first few seconds of polish. The experimental data fully support this mechanism. Based on this mechanism, process changes were made producing an order of magnitude reduction in micro-scratch related failures.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130612106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A planner 6.3 nm thin-body SOI MOSFET using tunnel epitaxy and nitrided gate oxides","authors":"S.S. Ahmed, G. Neudeck, J. Denton, M. Stidham","doi":"10.1109/UGIM.2003.1225743","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225743","url":null,"abstract":"A single-gate UTB SOI MOSFET was fabricated using tunnel epitaxy to form the silicon channel as thin as 6.3 nm. Experimental electrical measurements were conducted on a variety of devices, and the results are summarized. Low leakage currents were measured including gate leakage of 15 pA and device leakage of 1.1 pA. Measured I/spl square/V characteristics also included subthreshold slopes of 67 mV/dec., DIBL of 10 mV/V, and drive currents up to 280/spl square/A.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132687768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rectangular polysilicon diaphragms: fabrication and characterization","authors":"E. Woods, Zhiping Zhou","doi":"10.1109/UGIM.2003.1225769","DOIUrl":"https://doi.org/10.1109/UGIM.2003.1225769","url":null,"abstract":"Rectangular air-gap diaphragms are difficult to mechanically characterize. A standard fabrication process developed utilizing the smallest efficient etching access ports relative the diaphragm sizes, which ranged from 1406 /spl mu/m/sup 2/ to 36864 /spl mu/m/sup 2/. Polysilicon diaphragms having a thickness of 1 /spl mu/m above a 1 /spl mu/m air gap were fabricated on a silicon substrate and mechanically tested to determine the amount of force relative to geometry and size required to achieve maximum deflection and initial membrane sag using a standard Berkovich tip. The results showed that the force, maximum displacement, and unloading force curve fits followed power law distributions.","PeriodicalId":356452,"journal":{"name":"Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)","volume":"265 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122983475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}